/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 3.0.0 * stm32h743 version: 1.0 * stm32h743 authors: Aidan MacDonald * * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN_FMC_H__ #define __HEADERGEN_FMC_H__ #include "macro.h" #define STA_FMC (0x52004000) #define REG_FMC_BCR(_n1) st_reg(FMC_BCR(_n1)) #define STA_FMC_BCR(_n1) (0x52004000 + 0x0 + (_n1) * 0x8) #define STO_FMC_BCR(_n1) (0x0 + (_n1) * 0x8) #define STT_FMC_BCR(_n1) STIO_32_RW #define STN_FMC_BCR(_n1) FMC_BCR #define BP_FMC_BCR_BMAP 24 #define BM_FMC_BCR_BMAP 0x3000000 #define BF_FMC_BCR_BMAP(v) (((v) & 0x3) << 24) #define BFM_FMC_BCR_BMAP(v) BM_FMC_BCR_BMAP #define BF_FMC_BCR_BMAP_V(e) BF_FMC_BCR_BMAP(BV_FMC_BCR_BMAP__##e) #define BFM_FMC_BCR_BMAP_V(v) BM_FMC_BCR_BMAP #define BP_FMC_BCR_FMCEN 31 #define BM_FMC_BCR_FMCEN 0x80000000 #define BF_FMC_BCR_FMCEN(v) (((v) & 0x1) << 31) #define BFM_FMC_BCR_FMCEN(v) BM_FMC_BCR_FMCEN #define BF_FMC_BCR_FMCEN_V(e) BF_FMC_BCR_FMCEN(BV_FMC_BCR_FMCEN__##e) #define BFM_FMC_BCR_FMCEN_V(v) BM_FMC_BCR_FMCEN #define BP_FMC_BCR_WFDIS 21 #define BM_FMC_BCR_WFDIS 0x200000 #define BF_FMC_BCR_WFDIS(v) (((v) & 0x1) << 21) #define BFM_FMC_BCR_WFDIS(v) BM_FMC_BCR_WFDIS #define BF_FMC_BCR_WFDIS_V(e) BF_FMC_BCR_WFDIS(BV_FMC_BCR_WFDIS__##e) #define BFM_FMC_BCR_WFDIS_V(v) BM_FMC_BCR_WFDIS #define REG_FMC_SDCR(_n1) st_reg(FMC_SDCR(_n1)) #define STA_FMC_SDCR(_n1) (0x52004000 + 0x140 + (_n1) * 0x4) #define STO_FMC_SDCR(_n1) (0x140 + (_n1) * 0x4) #define STT_FMC_SDCR(_n1) STIO_32_RW #define STN_FMC_SDCR(_n1) FMC_SDCR #define BP_FMC_SDCR_RPIPE 13 #define BM_FMC_SDCR_RPIPE 0x6000 #define BF_FMC_SDCR_RPIPE(v) (((v) & 0x3) << 13) #define BFM_FMC_SDCR_RPIPE(v) BM_FMC_SDCR_RPIPE #define BF_FMC_SDCR_RPIPE_V(e) BF_FMC_SDCR_RPIPE(BV_FMC_SDCR_RPIPE__##e) #define BFM_FMC_SDCR_RPIPE_V(v) BM_FMC_SDCR_RPIPE #define BP_FMC_SDCR_SDCLK 10 #define BM_FMC_SDCR_SDCLK 0xc00 #define BF_FMC_SDCR_SDCLK(v) (((v) & 0x3) << 10) #define BFM_FMC_SDCR_SDCLK(v) BM_FMC_SDCR_SDCLK #define BF_FMC_SDCR_SDCLK_V(e) BF_FMC_SDCR_SDCLK(BV_FMC_SDCR_SDCLK__##e) #define BFM_FMC_SDCR_SDCLK_V(v) BM_FMC_SDCR_SDCLK #define BP_FMC_SDCR_CAS 7 #define BM_FMC_SDCR_CAS 0x180 #define BF_FMC_SDCR_CAS(v) (((v) & 0x3) << 7) #define BFM_FMC_SDCR_CAS(v) BM_FMC_SDCR_CAS #define BF_FMC_SDCR_CAS_V(e) BF_FMC_SDCR_CAS(BV_FMC_SDCR_CAS__##e) #define BFM_FMC_SDCR_CAS_V(v) BM_FMC_SDCR_CAS #define BP_FMC_SDCR_MWID 4 #define BM_FMC_SDCR_MWID 0x30 #define BF_FMC_SDCR_MWID(v) (((v) & 0x3) << 4) #define BFM_FMC_SDCR_MWID(v) BM_FMC_SDCR_MWID #define BF_FMC_SDCR_MWID_V(e) BF_FMC_SDCR_MWID(BV_FMC_SDCR_MWID__##e) #define BFM_FMC_SDCR_MWID_V(v) BM_FMC_SDCR_MWID #define BP_FMC_SDCR_NR 2 #define BM_FMC_SDCR_NR 0xc #define BF_FMC_SDCR_NR(v) (((v) & 0x3) << 2) #define BFM_FMC_SDCR_NR(v) BM_FMC_SDCR_NR #define BF_FMC_SDCR_NR_V(e) BF_FMC_SDCR_NR(BV_FMC_SDCR_NR__##e) #define BFM_FMC_SDCR_NR_V(v) BM_FMC_SDCR_NR #define BP_FMC_SDCR_NC 0 #define BM_FMC_SDCR_NC 0x3 #define BF_FMC_SDCR_NC(v) (((v) & 0x3) << 0) #define BFM_FMC_SDCR_NC(v) BM_FMC_SDCR_NC #define BF_FMC_SDCR_NC_V(e) BF_FMC_SDCR_NC(BV_FMC_SDCR_NC__##e) #define BFM_FMC_SDCR_NC_V(v) BM_FMC_SDCR_NC #define BP_FMC_SDCR_RBURST 12 #define BM_FMC_SDCR_RBURST 0x1000 #define BF_FMC_SDCR_RBURST(v) (((v) & 0x1) << 12) #define BFM_FMC_SDCR_RBURST(v) BM_FMC_SDCR_RBURST #define BF_FMC_SDCR_RBURST_V(e) BF_FMC_SDCR_RBURST(BV_FMC_SDCR_RBURST__##e) #define BFM_FMC_SDCR_RBURST_V(v) BM_FMC_SDCR_RBURST #define BP_FMC_SDCR_WP 9 #define BM_FMC_SDCR_WP 0x200 #define BF_FMC_SDCR_WP(v) (((v) & 0x1) << 9) #define BFM_FMC_SDCR_WP(v) BM_FMC_SDCR_WP #define BF_FMC_SDCR_WP_V(e) BF_FMC_SDCR_WP(BV_FMC_SDCR_WP__##e) #define BFM_FMC_SDCR_WP_V(v) BM_FMC_SDCR_WP #define BP_FMC_SDCR_NB 6 #define BM_FMC_SDCR_NB 0x40 #define BF_FMC_SDCR_NB(v) (((v) & 0x1) << 6) #define BFM_FMC_SDCR_NB(v) BM_FMC_SDCR_NB #define BF_FMC_SDCR_NB_V(e) BF_FMC_SDCR_NB(BV_FMC_SDCR_NB__##e) #define BFM_FMC_SDCR_NB_V(v) BM_FMC_SDCR_NB #define REG_FMC_SDTR(_n1) st_reg(FMC_SDTR(_n1)) #define STA_FMC_SDTR(_n1) (0x52004000 + 0x148 + (_n1) * 0x4) #define STO_FMC_SDTR(_n1) (0x148 + (_n1) * 0x4) #define STT_FMC_SDTR(_n1) STIO_32_RW #define STN_FMC_SDTR(_n1) FMC_SDTR #define BP_FMC_SDTR_TRCD 24 #define BM_FMC_SDTR_TRCD 0xf000000 #define BF_FMC_SDTR_TRCD(v) (((v) & 0xf) << 24) #define BFM_FMC_SDTR_TRCD(v) BM_FMC_SDTR_TRCD #define BF_FMC_SDTR_TRCD_V(e) BF_FMC_SDTR_TRCD(BV_FMC_SDTR_TRCD__##e) #define BFM_FMC_SDTR_TRCD_V(v) BM_FMC_SDTR_TRCD #define BP_FMC_SDTR_TRP 20 #define BM_FMC_SDTR_TRP 0xf00000 #define BF_FMC_SDTR_TRP(v) (((v) & 0xf) << 20) #define BFM_FMC_SDTR_TRP(v) BM_FMC_SDTR_TRP #define BF_FMC_SDTR_TRP_V(e) BF_FMC_SDTR_TRP(BV_FMC_SDTR_TRP__##e) #define BFM_FMC_SDTR_TRP_V(v) BM_FMC_SDTR_TRP #define BP_FMC_SDTR_TWR 16 #define BM_FMC_SDTR_TWR 0xf0000 #define BF_FMC_SDTR_TWR(v) (((v) & 0xf) << 16) #define BFM_FMC_SDTR_TWR(v) BM_FMC_SDTR_TWR #define BF_FMC_SDTR_TWR_V(e) BF_FMC_SDTR_TWR(BV_FMC_SDTR_TWR__##e) #define BFM_FMC_SDTR_TWR_V(v) BM_FMC_SDTR_TWR #define BP_FMC_SDTR_TRC 12 #define BM_FMC_SDTR_TRC 0xf000 #define BF_FMC_SDTR_TRC(v) (((v) & 0xf) << 12) #define BFM_FMC_SDTR_TRC(v) BM_FMC_SDTR_TRC #define BF_FMC_SDTR_TRC_V(e) BF_FMC_SDTR_TRC(BV_FMC_SDTR_TRC__##e) #define BFM_FMC_SDTR_TRC_V(v) BM_FMC_SDTR_TRC #define BP_FMC_SDTR_TRAS 8 #define BM_FMC_SDTR_TRAS 0xf00 #define BF_FMC_SDTR_TRAS(v) (((v) & 0xf) << 8) #define BFM_FMC_SDTR_TRAS(v) BM_FMC_SDTR_TRAS #define BF_FMC_SDTR_TRAS_V(e) BF_FMC_SDTR_TRAS(BV_FMC_SDTR_TRAS__##e) #define BFM_FMC_SDTR_TRAS_V(v) BM_FMC_SDTR_TRAS #define BP_FMC_SDTR_TXSR 4 #define BM_FMC_SDTR_TXSR 0xf0 #define BF_FMC_SDTR_TXSR(v) (((v) & 0xf) << 4) #define BFM_FMC_SDTR_TXSR(v) BM_FMC_SDTR_TXSR #define BF_FMC_SDTR_TXSR_V(e) BF_FMC_SDTR_TXSR(BV_FMC_SDTR_TXSR__##e) #define BFM_FMC_SDTR_TXSR_V(v) BM_FMC_SDTR_TXSR #define BP_FMC_SDTR_TMRD 0 #define BM_FMC_SDTR_TMRD 0xf #define BF_FMC_SDTR_TMRD(v) (((v) & 0xf) << 0) #define BFM_FMC_SDTR_TMRD(v) BM_FMC_SDTR_TMRD #define BF_FMC_SDTR_TMRD_V(e) BF_FMC_SDTR_TMRD(BV_FMC_SDTR_TMRD__##e) #define BFM_FMC_SDTR_TMRD_V(v) BM_FMC_SDTR_TMRD #define REG_FMC_SDCMR st_reg(FMC_SDCMR) #define STA_FMC_SDCMR (0x52004000 + 0x150) #define STO_FMC_SDCMR (0x150) #define STT_FMC_SDCMR STIO_32_RW #define STN_FMC_SDCMR FMC_SDCMR #define BP_FMC_SDCMR_MRD 9 #define BM_FMC_SDCMR_MRD 0x7ffe00 #define BF_FMC_SDCMR_MRD(v) (((v) & 0x3fff) << 9) #define BFM_FMC_SDCMR_MRD(v) BM_FMC_SDCMR_MRD #define BF_FMC_SDCMR_MRD_V(e) BF_FMC_SDCMR_MRD(BV_FMC_SDCMR_MRD__##e) #define BFM_FMC_SDCMR_MRD_V(v) BM_FMC_SDCMR_MRD #define BP_FMC_SDCMR_NRFS 5 #define BM_FMC_SDCMR_NRFS 0x1e0 #define BF_FMC_SDCMR_NRFS(v) (((v) & 0xf) << 5) #define BFM_FMC_SDCMR_NRFS(v) BM_FMC_SDCMR_NRFS #define BF_FMC_SDCMR_NRFS_V(e) BF_FMC_SDCMR_NRFS(BV_FMC_SDCMR_NRFS__##e) #define BFM_FMC_SDCMR_NRFS_V(v) BM_FMC_SDCMR_NRFS #define BP_FMC_SDCMR_MODE 0 #define BM_FMC_SDCMR_MODE 0x7 #define BF_FMC_SDCMR_MODE(v) (((v) & 0x7) << 0) #define BFM_FMC_SDCMR_MODE(v) BM_FMC_SDCMR_MODE #define BF_FMC_SDCMR_MODE_V(e) BF_FMC_SDCMR_MODE(BV_FMC_SDCMR_MODE__##e) #define BFM_FMC_SDCMR_MODE_V(v) BM_FMC_SDCMR_MODE #define BP_FMC_SDCMR_CTB1 4 #define BM_FMC_SDCMR_CTB1 0x10 #define BF_FMC_SDCMR_CTB1(v) (((v) & 0x1) << 4) #define BFM_FMC_SDCMR_CTB1(v) BM_FMC_SDCMR_CTB1 #define BF_FMC_SDCMR_CTB1_V(e) BF_FMC_SDCMR_CTB1(BV_FMC_SDCMR_CTB1__##e) #define BFM_FMC_SDCMR_CTB1_V(v) BM_FMC_SDCMR_CTB1 #define BP_FMC_SDCMR_CTB2 3 #define BM_FMC_SDCMR_CTB2 0x8 #define BF_FMC_SDCMR_CTB2(v) (((v) & 0x1) << 3) #define BFM_FMC_SDCMR_CTB2(v) BM_FMC_SDCMR_CTB2 #define BF_FMC_SDCMR_CTB2_V(e) BF_FMC_SDCMR_CTB2(BV_FMC_SDCMR_CTB2__##e) #define BFM_FMC_SDCMR_CTB2_V(v) BM_FMC_SDCMR_CTB2 #define REG_FMC_SDRTR st_reg(FMC_SDRTR) #define STA_FMC_SDRTR (0x52004000 + 0x154) #define STO_FMC_SDRTR (0x154) #define STT_FMC_SDRTR STIO_32_RW #define STN_FMC_SDRTR FMC_SDRTR #define BP_FMC_SDRTR_COUNT 1 #define BM_FMC_SDRTR_COUNT 0x3ffe #define BF_FMC_SDRTR_COUNT(v) (((v) & 0x1fff) << 1) #define BFM_FMC_SDRTR_COUNT(v) BM_FMC_SDRTR_COUNT #define BF_FMC_SDRTR_COUNT_V(e) BF_FMC_SDRTR_COUNT(BV_FMC_SDRTR_COUNT__##e) #define BFM_FMC_SDRTR_COUNT_V(v) BM_FMC_SDRTR_COUNT #define BP_FMC_SDRTR_REIE 14 #define BM_FMC_SDRTR_REIE 0x4000 #define BF_FMC_SDRTR_REIE(v) (((v) & 0x1) << 14) #define BFM_FMC_SDRTR_REIE(v) BM_FMC_SDRTR_REIE #define BF_FMC_SDRTR_REIE_V(e) BF_FMC_SDRTR_REIE(BV_FMC_SDRTR_REIE__##e) #define BFM_FMC_SDRTR_REIE_V(v) BM_FMC_SDRTR_REIE #define BP_FMC_SDRTR_CRE 0 #define BM_FMC_SDRTR_CRE 0x1 #define BF_FMC_SDRTR_CRE(v) (((v) & 0x1) << 0) #define BFM_FMC_SDRTR_CRE(v) BM_FMC_SDRTR_CRE #define BF_FMC_SDRTR_CRE_V(e) BF_FMC_SDRTR_CRE(BV_FMC_SDRTR_CRE__##e) #define BFM_FMC_SDRTR_CRE_V(v) BM_FMC_SDRTR_CRE #define REG_FMC_SDSR st_reg(FMC_SDSR) #define STA_FMC_SDSR (0x52004000 + 0x158) #define STO_FMC_SDSR (0x158) #define STT_FMC_SDSR STIO_32_RW #define STN_FMC_SDSR FMC_SDSR #define BP_FMC_SDSR_MODES2 3 #define BM_FMC_SDSR_MODES2 0x18 #define BF_FMC_SDSR_MODES2(v) (((v) & 0x3) << 3) #define BFM_FMC_SDSR_MODES2(v) BM_FMC_SDSR_MODES2 #define BF_FMC_SDSR_MODES2_V(e) BF_FMC_SDSR_MODES2(BV_FMC_SDSR_MODES2__##e) #define BFM_FMC_SDSR_MODES2_V(v) BM_FMC_SDSR_MODES2 #define BP_FMC_SDSR_MODES1 1 #define BM_FMC_SDSR_MODES1 0x6 #define BF_FMC_SDSR_MODES1(v) (((v) & 0x3) << 1) #define BFM_FMC_SDSR_MODES1(v) BM_FMC_SDSR_MODES1 #define BF_FMC_SDSR_MODES1_V(e) BF_FMC_SDSR_MODES1(BV_FMC_SDSR_MODES1__##e) #define BFM_FMC_SDSR_MODES1_V(v) BM_FMC_SDSR_MODES1 #define BP_FMC_SDSR_RE 0 #define BM_FMC_SDSR_RE 0x1 #define BF_FMC_SDSR_RE(v) (((v) & 0x1) << 0) #define BFM_FMC_SDSR_RE(v) BM_FMC_SDSR_RE #define BF_FMC_SDSR_RE_V(e) BF_FMC_SDSR_RE(BV_FMC_SDSR_RE__##e) #define BFM_FMC_SDSR_RE_V(v) BM_FMC_SDSR_RE #endif /* __HEADERGEN_FMC_H__*/