name "x1000" title "Ingenic X1000" isa "mips" version "1.0" author "Aidan MacDonald" node LCD { title "LCD controller" addr 0xb3050000 reg CFG 0x00 { bit 17 INVDAT } reg CTRL 0x30 { fld 30 28 BURST { enum 4WORD 0; enum 8WORD 1; enum 16WORD 2; enum 32WORD 3; enum 64WORD 4; } bit 13 EOFM bit 12 SOFM bit 10 IFUM bit 7 QDM bit 6 BEDN bit 5 PEDN bit 3 ENABLE fld 2 0 BPP { enum 15BIT_OR_16BIT 4 enum 18BIT_OR_24BIT 5 enum 24BIT_COMPRESSED 6 enum 30BIT 7 } } reg STATE 0x34 { bit 7 QD bit 5 EOF bit 4 SOF bit 2 IFU } reg OSDCTRL 0x104 reg BGC 0x10c reg DAH 0x10 reg DAV 0x14 reg VAT 0x0c reg VSYNC 0x04 reg HSYNC 0x08 reg IID 0x38 reg DA 0x40 reg MCFG 0xa0 { # other fields are useless according to Ingenic field 9 8 CWIDTH { enum 16BIT_OR_9BIT 0 enum 8BIT 1 enum 18BIT 2 enum 24BIT 3 } } reg MCFG_NEW 0xb8 { field 15 13 DWIDTH { enum 8BIT 0 enum 9BIT 1 enum 16BIT 2 enum 18BIT 3 enum 24BIT 4 } field 9 8 DTIMES { enum 1TIME 0 enum 2TIME 1 enum 3TIME 2 } bit 11 6800_MODE bit 10 CMD_9BIT bit 5 CSPLY bit 4 RSPLY bit 3 CLKPLY bit 2 DTYPE { enum SERIAL 1; enum PARALLEL 0 } bit 1 CTYPE { enum SERIAL 1; enum PARALLEL 0 } bit 0 FMT_CONV } reg MCTRL 0xa4 { bit 10 NARROW_TE bit 9 TE_INV bit 8 NOT_USE_TE bit 7 DCSI_SEL bit 6 MIPI_SLCD bit 4 FAST_MODE bit 3 GATE_MASK bit 2 DMA_MODE bit 1 DMA_START bit 0 DMA_TX_EN } reg MSTATE 0xa8 { fld 31 16 LCD_ID bit 0 BUSY } reg MDATA 0xac { fld 31 30 TYPE { enum CMD 1; enum DAT 0 } fld 23 0 DATA } reg WTIME 0xb0 { fld 31 24 DHTIME fld 23 16 DLTIME fld 15 8 CHTIME fld 7 0 CLTIME } reg TASH 0xb4 { fld 15 8 TAH fld 7 0 TAS } reg SMWT 0xbc } node AIC { title "Audio interface controller" addr 0xb0020000 reg CFG 0x00 { fld 27 24 RFTH fld 20 16 TFTH bit 12 MSB bit 10 IBCKD bit 9 ISYNCD bit 8 DMODE bit 7 CDC_SLAVE bit 6 LSMP bit 5 ICDC bit 4 AUSEL bit 3 RST bit 2 BCKD bit 1 SYNCD bit 0 ENABLE } reg CCR 0x04 { bit 28 PACK16 fld 26 24 CHANNEL { enum MONO 0; enum STEREO 1 } fld 21 19 OSS { enum 8BIT 0; enum 16BIT 1; enum 18BIT 2; enum 20BIT 3; enum 24BIT 4 } fld 18 16 ISS { enum 8BIT 0; enum 16BIT 1; enum 18BIT 2; enum 20BIT 3; enum 24BIT 4 } bit 15 RDMS bit 14 TDMS bit 11 M2S bit 10 ENDSW bit 9 ASVTSU bit 8 TFLUSH bit 7 RFLUSH bit 6 EROR bit 5 ETUR bit 4 ERFS bit 3 ETFS bit 2 ENLBF bit 1 ERPL bit 0 EREC } reg I2SCR 0x10 { bit 17 RFIRST bit 16 SWLH bit 13 ISTPBK bit 12 STPBK bit 4 ESCLK bit 0 AMSL } reg SR 0x14 { fld 29 24 RFL bit 13 8 TFL bit 6 ROR bit 5 TUR bit 4 RFS bit 3 TFS } reg I2SSR 0x1c { bit 5 CHBSY bit 4 TBSY bit 3 RBSY bit 2 BSY } reg I2SDIV 0x30 reg DR 0x34 reg SPENA 0x80 reg SPCTRL 0x84 { bit 15 DMA_EN bit 14 D_TYPE bit 13 SIGN_N bit 12 INVALID bit 11 SFT_RST bit 10 SPDIF_I2S bit 1 M_TRIG bit 0 M_FFUR } reg SPSTATE 0x88 { fld 14 8 FIFO_LEVEL bit 7 BUSY bit 1 F_TRIG bit 0 F_FFUR } reg SPCFG1 0x8c { bit 17 INIT_LEVEL bit 16 ZERO_VALID fld 13 12 TRIG fld 11 8 SRC_NUM fld 7 4 CH1_NUM fld 3 0 CH2_NUM } reg SPCFG2 0x90 { fld 29 26 FS fld 25 22 ORG_FRQ fld 21 19 SAMPL_WL bit 18 MAX_WL fld 17 16 CLK_ACU fld 15 8 CAT_CODE fld 7 6 CH_MD bit 3 PRE bit 2 COPY_N bit 1 AUDIO_N bit 0 CON_PRO } reg SPFIFO 0x94 reg RGADW 0xa4 { bit 31 ICRST bit 16 RGWR fld 14 8 ADDR fld 7 0 DATA } reg RGDATA 0xa8 { bit 8 IRQ fld 7 0 DATA } } node PCM { title "PCM interface controller" addr 0xb0071000 reg CTL 0x00 { bit 9 ERDMA bit 8 ETDMA bit 7 LSMP bit 6 ERPL bit 5 EREC bit 4 FLUSH bit 3 RST bit 1 CLKEN bit 0 PCMEN } reg CFG 0x04 { fld 14 13 SLOT bit 12 ISS bit 11 OSS bit 10 IMSBPOS bit 9 OMSBPOS fld 8 5 RFTH fld 4 1 TFTH bit 0 PCMMOD } reg DP 0x08 reg INTC 0x0c { bit 3 ETFS bit 2 ETUR bit 1 ERFS bit 0 EROR } reg INTS 0x10 { bit 14 RSTS fld 13 9 TFL bit 8 TFS bit 7 TUR bit 6 2 RFL bit 1 RFS bit 0 ROR } reg DIV 0x14 { fld 16 11 SYNL fld 10 6 SYNDIV fld 5 0 CLKDIV } } node DDRC { title "DDR controller AHB2 group" desc "note: incomplete, only lists registers used by DDR init code" addr 0xb34f0000 reg STATUS 0x00 reg CFG 0x04 reg CTRL 0x08 reg TIMING1 0x60 reg TIMING2 0x64 reg TIMING3 0x68 reg TIMING4 0x6c reg TIMING5 0x70 reg TIMING6 0x74 reg REFCNT 0x18 reg MMAP0 0x24 reg MMAP1 0x28 reg DLP 0xbc reg REMAP1 0x9c reg REMAP2 0xa0 reg REMAP3 0xa4 reg REMAP4 0xa8 reg REMAP5 0xac reg AUTOSR_CNT 0x308 reg AUTOSR_EN 0x304 } node DDRC_APB { title "DDR controller APB group" desc "note: incomplete, only lists registers used by DDR init code" addr 0xb3012000 reg CLKSTP_CFG 0x68 reg PHYRST_CFG 0x80 } node DDRPHY { title "DDR PHY group" desc "note: incomplete, only lists registers used by DDR init code" addr 0xb3011000 reg PIR 0x04 reg PGCR 0x08 reg PGSR 0x0c reg DLLGCR 0x10 reg ACDLLCR 0x14 reg PTR0 0x18 reg PTR1 0x1c reg PTR2 0x20 reg ACIOCR 0x24 reg DXCCR 0x28 reg DSGCR 0x2c reg DCR 0x30 reg DTPR0 0x34 reg DTPR1 0x38 reg DTPR2 0x3c reg MR0 0x40 reg MR1 0x44 reg MR2 0x48 reg MR3 0x4c reg DTAR 0x54 reg DXGCR { instance 0x1c0 0x40 4 } } node SFC { title "SPI flash controller" addr 0xb3440000 reg GLB 0x00 { bit 13 TRAN_DIR { enum READ 0; enum WRITE 1 } fld 12 7 THRESHOLD bit 6 OP_MODE { enum SLAVE 0; enum DMA 1 } fld 5 3 PHASE_NUM bit 2 WP_EN bit 1 0 BURST_MD { enum INCR4 0; enum INCR8 1; enum INCR16 2; enum INCR32 3 } } reg DEV_CONF 0x04 { fld 17 16 SMP_DELAY bit 15 CMD_TYPE { enum 8BITS 0; enum 16BITS 1 } fld 14 13 STA_TYPE { enum 1BYTE 0; enum 2BYTE 1; enum 3BYTE 2; enum 4BYTE 3 } fld 12 11 THOLD fld 10 9 TSETUP fld 8 5 TSH bit 4 CPHA bit 3 CPOL bit 2 CE_DL bit 1 HOLD_DL bit 0 WP_DL } reg DEV_STA_EXP 0x08 reg DEV_STA_RT 0x0c reg DEV_STA_MSK 0x10 reg TRAN_CONF { instance 0x14 0x04 6 fld 31 29 MODE fld 28 26 ADDR_WIDTH bit 25 POLL_EN bit 24 CMD_EN bit 23 PHASE_FMT fld 22 17 DUMMY_BITS bit 16 DATA_EN fld 15 0 COMMAND } reg TRAN_LENGTH 0x2c reg DEV_ADDR { instance 0x30 0x04 6 } reg DEV_PLUS { instance 0x48 0x40 6 } reg MEM_ADDR 0x60 reg TRIG 0x64 { bit 2 FLUSH bit 1 STOP bit 0 START } reg SR 0x68 { fld 22 16 FIFO_NUM fld 6 5 BUSY bit 4 END bit 3 TREQ bit 2 RREQ bit 1 OVER bit 0 UNDER } reg SCR 0x6c { bit 4 CLR_END bit 3 CLR_TREQ bit 2 CLR_RREQ bit 1 CLR_OVER bit 0 CLR_UNDER } reg INTC 0x70 { bit 4 MSK_END bit 3 MSK_TREQ bit 2 MSK_RREQ bit 1 MSK_OVER bit 0 MSK_UNDER } reg FSM 0x74 { fld 19 16 STATE_AHB fld 15 11 STATE_SPI fld 9 6 STATE_CLK fld 5 3 STATE_DMAC bit 2 0 STATE_RMC } reg CGE 0x78 { bit 5 SFC bit 4 FIFO bit 3 DMA bit 2 RMC bit 1 SPI bit 0 REG } reg DATA 0x1000 } node CPM { title "Clock, Reset and Power Manager" addr 0xb0000000 reg CCR 0x00 { fld 31 30 SEL_SRC { enum STOP 0; enum EXCLK 1; enum APLL 2; } fld 29 28 SEL_CPLL { enum STOP 0; enum SCLK_A 1; enum MPLL 2; } fld 27 26 SEL_H0PLL { enum STOP 0; enum SCLK_A 1; enum MPLL 2; } fld 25 24 SEL_H2PLL { enum STOP 0; enum SCLK_A 1; enum MPLL 2; } bit 23 GATE_SCLKA bit 22 CE_CPU bit 21 CE_AHB0 bit 20 CE_AHB2 fld 19 16 PDIV fld 15 12 H2DIV fld 11 8 H0DIV fld 7 4 L2DIV fld 3 0 CDIV } reg CSR 0xd4 { bit 31 SRC_MUX bit 30 CPU_MUX bit 29 AHB0_MUX bit 28 AHB2_MUX bit 27 DDR_MUX bit 2 H2DIV_BUSY bit 1 H0DIV_BUSY bit 0 CDIV_BUSY } reg DDRCDR 0x2c { fld 31 30 CLKSRC { enum STOP 0; enum SCLK_A 1; enum MPLL 2; } bit 29 CE bit 28 BUSY bit 27 STOP bit 26 GATE_EN bit 25 CHANGE_EN bit 24 FLAG fld 3 0 CLKDIV } reg MACCDR 0x54 { bit 31 CLKSRC { enum SCLK_A 0; enum MPLL 1; } bit 29 CE bit 28 BUSY bit 27 STOP fld 7 0 CLKDIV } reg I2SCDR 0x60 { bit 31 PCS { enum SCLK_A 0; enum MPLL 1; } bit 30 CS { enum EXCLK 0; enum PLL 1; } bit 29 CE fld 21 13 DIV_M fld 12 0 DIV_N } reg I2SCDR1 0x70 reg LPCDR 0x64 { bit 31 CLKSRC { enum SCLK_A 0; enum MPLL 1; } bit 28 CE bit 27 BUSY bit 26 STOP fld 7 0 CLKDIV } reg MSC0CDR 0x68 { bit 31 CLKSRC { enum SCLK_A 0; enum MPLL 1; } bit 29 CE bit 28 BUSY bit 27 STOP bit 15 S_CLK0_SEL { enum 90DEG 0; enum 180DEG 1; } fld 7 0 CLKDIV } reg MSC1CDR 0xa4 { bit 29 CE bit 28 BUSY bit 27 STOP bit 15 S_CLK1_SEL { enum 90DEG 0; enum 180DEG 1; } fld 7 0 CLKDIV } reg USBCDR 0x50 { fld 31 30 CLKSRC { enum EXCLK 0; enum SCLK_A 2; enum MPLL 3; } bit 29 CE bit 28 BUSY bit 27 STOP # PHY_GATE bit undocumented but present in Ingenic kernel sources, # it's not clear it does anything. bit 26 PHY_GATE fld 7 0 CLKDIV } reg SSICDR 0x74 { bit 31 SFC_CS { enum SCLK_A 0; enum MPLL 1 } bit 30 SSI_CS { enum EXCLK 0; enum HALF_SFC 1 } bit 29 CE bit 28 BUSY bit 27 STOP fld 7 0 CLKDIV } reg CIMCDR 0x7c { bit 31 CLKSRC { enum SCLK_A 1; enum MPLL 1 } bit 29 CE bit 28 BUSY bit 27 STOP fld 7 0 CLKDIV } reg PCMCDR 0x84 { # Hardware manual says this is the correct definition, but based # on Ingenic's sources, the format is actually like I2SCDR. #fld 31 30 CLKSRC { enum SCLK_A 0; enum EXCLK 1; enum MPLL 2 } # Note this format hasn't been verified to work because none of # the X1000 targets are using a PCM interface. bit 31 PCS { enum SCLK_A 0; enum MPLL 1; } bit 30 CS { enum EXCLK 0; enum PLL 1; } bit 29 CE fld 21 13 DIV_M fld 12 0 DIV_N } reg PCMCDR1 0xe0 { bit 31 N_EN bit 30 D_EN fld 12 0 DIV_D } reg INTR 0xb0 { bit 1 VBUS bit 0 ADEV } reg INTR_EN 0xb4 { bit 1 VBUS bit 0 ADEV } reg DRCG 0xd0 reg SCRATCH_PROT 0x38 reg SCRATCH 0x34 reg USBPCR 0x3c { bit 31 USB_MODE { enum USB 0; enum OTG 1; } bit 30 AVLD_REG fld 29 28 IDPULLUP_MASK { enum ALWAYS 2; enum ALWAYS_SUSPEND 1; enum FROM_OTG 0; } bit 27 INCR_MASK bit 26 TXRISETUNE bit 25 COMMONONN bit 24 VBUSVLDEXT bit 23 VBUSVLDEXTSEL bit 22 POR bit 21 SIDDQ bit 20 OTG_DISABLE fld 19 17 COMPDISTUNE fld 16 14 OTGTUNE fld 13 11 SQRXTUNE fld 10 7 TXFSLSTUNE bit 6 TXPREEMPHTUNE fld 5 4 TXHSXVTUNE fld 3 0 TXVREFTUNE } reg USBRDT 0x40 { bit 26 HB_MASK bit 25 VBFIL_LD_EN bit 24 IDDIG_EN bit 23 IDDIG_REG fld 22 0 RDT } reg USBVBFIL 0x44 { fld 31 16 IDDIGFIL fld 15 0 VBFIL } reg USBPCR1 0x48 { bit 31 BVLD_REG fld 27 26 REFCLK_SEL { enum CLKCORE 2; enum EXTERNAL 1; enum CRYSTAL 0 } fld 25 24 REFCLK_DIV { enum 48MHZ 2; enum 24MHZ 1; enum 12MHZ 0 } bit 21 PORT_RST bit 19 WORD_IF { enum 16BIT 1; enum 8BIT 0 } } reg APCR 0x10 { bit 31 BS fld 30 24 PLLM fld 22 18 PLLN fld 17 16 PLLOD bit 15 LOCK bit 10 ON bit 9 BYPASS bit 8 ENABLE fld 7 0 PLLST } reg MPCR 0x14 { bit 31 BS fld 30 24 PLLM fld 22 18 PLLN fld 17 16 PLLOD bit 7 ENABLE bit 6 BYPASS bit 1 LOCK bit 0 ON } reg LCR 0x04 { fld 19 8 PST fld 1 0 LPM { enum IDLE 0; enum SLEEP 1 } } reg PSWC0ST 0x90 reg PSWC1ST 0x94 reg PSWC2ST 0x98 reg PSWC3ST 0x9c reg CLKGR 0x20 { desc "Clock gate register" bit 31 DDR bit 30 CPU_BIT # can't be called CPU because Rockbox #defines that bit 29 AHB0 bit 28 APB0 bit 27 RTC bit 26 PCM bit 25 MAC bit 24 AES bit 23 LCD bit 22 CIM bit 21 PDMA bit 20 OST bit 19 SSI bit 18 TCU bit 17 DMIC bit 16 UART2 bit 15 UART1 bit 14 UART0 bit 12 JPEG bit 11 AIC bit 9 I2C2 bit 8 I2C1 bit 7 I2C0 bit 6 SCC bit 5 MSC1 bit 4 MSC0 bit 3 OTG bit 2 SFC bit 1 EFUSE } reg SRBC 0xc4 { bit 31 JPEG_SR bit 30 JPEG_STOP bit 29 JPEG_ACK bit 25 LCD_SR bit 24 LCD_STOP bit 23 LCD_ACK bit 21 CIM_STOP bit 20 CIM_ACK bit 15 CPU_STOP bit 14 CPU_ACK bit 12 OTG_SR bit 8 AHB2_STOP bit 7 AHB2_ACK bit 6 DDR_STOP bit 5 DDR_ACK } reg OPCR 0x24 { bit 31 IDLE_DIS bit 30 MASK_INT bit 29 MASK_VPU bit 28 GATE_SCLK_A_BUS bit 25 L2C_PD bit 24 REQ_MODE bit 23 GATE_USBPHY_CLK bit 22 DIS_STOP_MUX fld 19 8 O1ST bit 7 SPENDN0 bit 6 SPENDN1 bit 5 CPU_MODE bit 4 O1SE bit 3 PD bit 2 ERCS bit 1 BUS_MODE } reg RSR 0x08 { bit 3 HR bit 2 P0R bit 1 WR bit 0 PR } } node TCU { title "Timer/counter unit" addr 0xb0002000 reg STATUS 0xf0 { variant set 4; variant clr 8 } reg STOP 0x1c { variant set 0x10; variant clr 0x20 } reg ENABLE 0x10 { variant set 4; variant clr 8 } reg FLAG 0x20 { variant set 4; variant clr 8 } reg MASK 0x30 { variant set 4; variant clr 8 } reg CMP_FULL { desc "called Data FULL by Ingenic" instance 0x40 0x10 8 } reg CMP_HALF { desc "called Data HALF by Ingenic" instance 0x44 0x10 8 } reg COUNT { instance 0x48 0x10 8 } reg CTRL { instance 0x4c 0x10 8 bit 11 BYPASS bit 10 CLRZ bit 9 SHUTDOWN { enum GRACEFUL 0; enum ABRUPT 1; } bit 8 INIT_LVL bit 7 PWM_EN bit 6 PWM_IN_EN fld 5 3 PRESCALE { enum BY_1 0; enum BY_4 1; enum BY_16 2; enum BY_64 3; enum BY_256 4; enum BY_1024 5; } fld 2 0 SOURCE { enum EXT 4; enum RTC 2; enum PCLK 1; } } } node OST { title "Operating system timer" addr 0xb2000000 reg CTRL 0x00 { field 3 2 PRESCALE2 { enum BY_1 0; enum BY_4 1; enum BY_16 2; } field 1 0 PRESCALE1 { enum BY_1 0; enum BY_4 1; enum BY_16 2; } } reg ENABLE 0x04 { variant set 0x30 variant clr 0x34 bit 0 OST1 bit 1 OST2 } reg CLEAR 0x08 { bit 0 OST1 bit 1 OST2 } reg 1FLG 0x0c reg 1MSK 0x10 reg 1DFR 0x14 reg 1CNT 0x18 reg 2CNTH 0x1c reg 2CNTL 0x20 reg 2CNTHB 0x24 } node INTC { title "Interrupt controller" # Documented address in Ingenic's manual is a typo (= GPIO base address). # This is the correct address from their Linux source. addr 0xb0001000 reg SRC { instance 0x00 0x20 2 } reg MSK { instance 0x04 0x20 2; variant set 4; variant clr 8 } reg PND { instance 0x10 0x20 2 } } node WDT { title "Watchdog timer" addr 0xb0002000 reg DATA 0x00 reg ENABLE 0x04 reg COUNT 0x08 reg CTRL 0x0c { field 5 3 PRESCALE { enum BY_1 0; enum BY_4 1; enum BY_16 2; enum BY_64 3; enum BY_256 4; enum BY_1024 5; } field 2 0 SOURCE { enum EXT 4; enum RTC 2; enum PLCK 1; } } } node DMA { title "DMA controller" addr 0xb3421000 reg CTRL 0x00 { bit 31 FMSC bit 30 FSSI bit 29 FTSSI bit 28 FUART bit 27 FAIC bit 3 HALT bit 2 AR bit 0 ENABLE } reg IRQP 0x04 reg DB 0x08 { variant set 4 } reg DIP 0x10 reg DIC 0x14 } node DMA_CHN { title "DMA channel registers" instance 0xb3420000 0x20 8 reg SA 0x00 reg TA 0x04 reg TC 0x08 { fld 31 24 DOA fld 23 0 CNT } reg RT 0x0c { field 5 0 TYPE { enum DMIC_RX 5 enum I2S_TX 6 enum I2S_RX 7 enum AUTO 8 enum UART2_TX 16 enum UART2_RX 17 enum UART1_TX 18 enum UART1_RX 19 enum UART0_TX 20 enum UART0_RX 21 enum SSI_TX 22 enum SSI_RX 23 enum MSC0_TX 26 enum MSC0_RX 27 enum MSC1_TX 28 enum MSC1_RX 29 enum PCM_TX 32 enum PCM_RX 33 enum I2C0_TX 36 enum I2C0_RX 37 enum I2C1_TX 38 enum I2C1_RX 39 enum I2C2_TX 40 enum I2C2_RX 41 } } reg CS 0x10 { bit 31 NDES bit 30 DES8 fld 15 8 CDOA bit 4 AR bit 3 TT bit 2 HLT bit 0 CTE } reg CM 0x14 { bit 23 SAI bit 22 DAI fld 19 16 RDIL fld 15 14 SP { enum 32BIT 0; enum 8BIT 1; enum 16BIT 2 } fld 13 12 DP { enum 32BIT 0; enum 8BIT 1; enum 16BIT 2 } fld 10 8 TSZ { enum 32BIT 0; enum 8BIT 1; enum 16BIT 2; enum 16BYTE 3; enum 32BYTE 4; enum 64BYTE 5; enum 128BYTE 6; enum AUTO 7; } bit 2 STDE bit 1 TIE bit 0 LINK } reg DA 0x18 { fld 31 12 DBA fld 11 4 DOA } reg SD 0x1c { fld 31 16 TSD fld 15 0 SSD } } node RTC { title "Realtime clock" addr 0xb0003000 reg CR 0x00 { bit 7 WRDY bit 6 1HZ bit 5 1HZIE bit 4 AF bit 3 AIE bit 2 AE bit 1 SELEXC bit 0 ENABLE } reg SR 0x04 reg SAR 0x08 reg GR 0x0c { bit 31 LOCK fld 25 16 ADJC fld 15 0 NC1HZ } reg HCR 0x20 reg HWFCR 0x24 reg HRCR 0x28 reg HWCR 0x2c { fld 31 3 EPDET bit 1 EALM } reg HWRSR 0x30 { bit 8 APD bit 5 HR bit 4 PPR bit 1 PIN bit 0 ALM } reg HSPR 0x34 reg WENR 0x3c { bit 31 WEN bit 15 0 WENPAT } reg WKUPPINCR 0x48 } node EFUSE { title "EFUSE interface" instance 0xb3540000 reg CTRL 0x00 { fld 27 21 ADDR fld 20 16 LENGTH bit 15 PG_EN bit 1 WR_EN bit 0 RD_EN } reg CFG 0x04 { bit 31 INT_EN fld 21 20 RD_AJD fld 18 16 RD_STROBE fld 13 12 WR_ADJ fld 8 0 WR_STROBE } reg STATE 0x08 { bit 23 UK_PRT bit 22 NKU_PRT bit 21 EXKEY_EN bit 15 CUSTID_PRT bit 14 CHIPID_PRT bit 12 SECBOOT_PRT bit 11 DIS_JTAG bit 8 SECBOOT_EN bit 1 WR_DONE bit 0 RD_DONE } reg DATA { instance 0x0c 0x04 8 } } node GPIO { title "General purpose I/O" addr 0xb0010000 # Note: only instances 0-3 and 7 are instantiated in hardware reg PIN { instance 0x00 0x100 8 } reg INT { instance 0x10 0x100 8; variant set 4; variant clr 8 } reg MSK { instance 0x20 0x100 8; variant set 4; variant clr 8 } reg PAT1 { instance 0x30 0x100 8; variant set 4; variant clr 8 } reg PAT0 { instance 0x40 0x100 8; variant set 4; variant clr 8 } reg FLAG { instance 0x50 0x100 8; variant clr 8 } reg PULL { instance 0x70 0x100 8; variant set 4; variant clr 8 } node C_GLITCH { desc "GPIO port C: glitch filter registers" addr 0x200 reg CFG0 0x800 { variant set 4; variant clr 8 } reg CFG1 0x810 { variant set 4; variant clr 8 } reg CFG2 0x820 { variant set 4; variant clr 8 } reg CFG3 0x830 { variant set 4; variant clr 8 } } reg Z_GID2LD { desc "GPIO port Z: atomic load register" addr 0x7f0 } } node I2C { title "I2C bus controller" instance 0xb0050000 0x1000 3 reg CON 0x00 { bit 6 SLVDIS bit 5 RESTART bit 4 MATP bit 3 SATP fld 2 1 SPEED { enum 100K 1; enum 400K 2; } bit 0 MD } reg DC 0x10 { bit 10 RESTART bit 9 STOP bit 8 CMD fld 7 0 DAT } reg INTST 0x2c { bit 11 GC bit 10 STT bit 9 STP bit 8 ACT bit 7 RXDN bit 6 TXABT bit 5 RDREQ bit 4 TXEMP bit 3 TXOF bit 2 RXFL bit 1 RXOF bit 0 RXUF } reg INTMSK 0x30 { bit 11 GC bit 10 STT bit 9 STP bit 8 ACT bit 7 RXDN bit 6 TXABT bit 5 RDREQ bit 4 TXEMP bit 3 TXOF bit 2 RXFL bit 1 RXOF bit 0 RXUF } reg RINTST 0x34 { bit 11 GC bit 10 STT bit 9 STP bit 8 ACT bit 7 RXDN bit 6 TXABT bit 5 RDREQ bit 4 TXEMP bit 3 TXOF bit 2 RXFL bit 1 RXOF bit 0 RXUF } reg ENABLE 0x6c { bit 1 ABORT bit 0 ACTIVE } reg STATUS 0x70 { bit 6 SLVACT bit 5 MSTACT bit 4 RFF bit 3 RFNE bit 2 TFE bit 1 TFNF bit 0 ACT } reg ENBST 0x9c { bit 2 SLVRDLST bit 1 SLVDISB bit 0 ACTIVE } reg TAR 0x04 { bit 12 10BITS bit 11 SPECIAL bit 10 GC_OR_START fld 9 0 ADDR } reg SAR 0x08 reg SHCNT 0x14 reg SLCNT 0x18 reg FHCNT 0x1c reg FLCNT 0x20 reg RXTL 0x38 reg TXTL 0x3c reg TXFLR 0x74 reg RXFLR 0x78 reg SDAHD 0x7c reg ABTSRC 0x80 reg DMACR 0x88 reg DMATDLR 0x8c reg DMARDLR 0x90 reg SDASU 0x94 reg ACKGC 0x98 reg FLT 0xa0 reg CINT 0x40 reg CRXUF 0x44 reg CRXOF 0x48 reg CTXOF 0x4c reg CRXREQ 0x50 reg CTXABT 0x54 reg CRXDN 0x58 reg CACT 0x5c reg CSTP 0x60 reg CSTT 0x64 reg CGC 0x68 } node SSI { title "Synchronous serial interface" instance 0xb0043000 reg DR 0x00 reg CR0 0x04 { fld 19 18 TENDIAN fld 17 16 RENDIAN bit 15 SSIE bit 14 TIE bit 13 RIE bit 12 TEIE bit 11 REIE bit 10 LOOP bit 9 RFINE bit 8 RFINC bit 7 EACLRUN bit 6 FSEL bit 4 VRCNT bit 3 TFMODE bit 2 TFLUSH bit 1 RFLUSH bit 0 DISREV } reg CR1 0x08 { fld 31 30 FRMHL fld 29 28 TFVCK fld 27 26 TCKFI bit 24 ITFRM bit 23 UNFIN fld 21 20 FMAT fld 19 16 TTRG fld 15 12 MCOM fld 11 8 RTRG fld 7 3 FLEN bit 1 PHA bit 0 POL } reg SR 0x0c { fld 24 16 TFIFO_NUM fld 15 8 RFIFO_NUM bit 7 END bit 6 BUSY bit 5 TFF bit 4 RFE bit 3 TFHE bit 2 RFHF bit 1 UNDR bit 0 OVER } reg ITR 0x10 { bit 15 CNTCLK fld 14 0 IVLTM } reg ICR 0x14 reg GR 0x18 reg RCNT 0x1c } node UART { title "UART controller" instance 0xb0030000 0x1000 3 # Note there is some hardware multiplexing controlled by the # ULCR register going on here which is why some registers share # the same address. reg URBR 0x00 reg UTHR 0x00 reg UDLLR 0x00 reg UDLHR 0x04 reg UIER 0x04 { bit 4 RTOIE bit 3 MSIE bit 2 RLSIE bit 1 TDRIE bit 0 RDRIE } reg UIIR 0x08 { fld 7 6 FFMSEL { enum NON_FIFO_MODE 0; enum FIFO_MODE 1; } fld 3 1 INID { enum MODEM_STATUS 0; enum TRANSMIT_DATA_REQ 1; enum RECEIVE_DATA_READY 2 enum RECEIVE_LINE_STATUS 3; enum RECEIVE_TIME_OUT 6 } bit 0 INPEND } reg UFCR 0x08 { fld 7 6 RDTR { enum 1BYTE 0; enum 16BYTE 1; enum 32BYTE 2; enum 60BYTE 3; } bit 4 UME bit 3 DME bit 2 TFRT bit 1 RFRT bit 0 FME } reg ULCR 0x0c { bit 7 DLAB bit 6 SBK bit 5 STPAR bit 4 PARM { enum ODD 0; enum EVEN 1; } bit 3 PARE bit 2 SBLS { enum 1_STOP_BIT 0; enum 2_STOP_BITS 1; } fld 1 0 WLS { enum 5BITS 0; enum 6BITS 1; enum 7BITS 2; enum 8BITS 3; } } reg UMCR 0x10 { bit 7 MDCE bit 6 FCM bit 4 LOOP bit 1 RTS } reg ULSR 0x14 { bit 7 FIFOE bit 6 TEMP bit 5 TDRQ bit 4 BI bit 3 FMER bit 2 PARER bit 1 OVER bit 0 DRY } reg UMSR 0x18 { bit 4 CTS bit 0 CCTS } reg USPR 0x1c reg ISR 0x20 { bit 4 RDPL bit 3 TDPL bit 2 XMODE bit 1 RCVEIR bit 0 XMITIR } reg UMR 0x24 reg UACR 0x28 reg URCR 0x40 reg UTCR 0x44 } node MSC { title "MMC/SD/CE-ATA controller" instance 0xb3450000 0x10000 2 reg CTRL 0x00 { bit 15 SEND_CCSD bit 14 SEND_AS_CCSD bit 7 EXIT_MULTIPLE bit 6 EXIT_TRANSFER bit 5 START_READ_WAIT bit 4 STOP_READ_WAIT bit 3 RESET bit 2 START_OP fld 1 0 CLOCK { enum DO_NOTHING 0; enum STOP 1; enum START 2; } } reg STAT 0x04 { bit 31 AUTO_CMD12_DONE fld 28 24 PINS bit 20 BCE bit 19 BDE bit 18 BAE bit 17 BAR bit 16 DMAEND bit 15 IS_RESETTING bit 14 SDIO_INT_ACTIVE bit 13 PROG_DONE bit 12 DATA_TRAN_DONE bit 11 END_CMD_RES bit 10 DATA_FIFO_AFULL bit 9 IS_READ_WAIT bit 8 CLOCK_EN bit 7 DATA_FIFO_FULL bit 6 DATA_FIFO_EMPTY bit 5 CRC_RES_ERROR bit 4 CRC_READ_ERROR fld 3 2 CRC_WRITE_ERROR { enum NONE 0; enum BADDATA 1; enum NOCRC 2 } bit 1 TIME_OUT_RES bit 0 TIME_OUT_READ } reg CMDAT 0x0c { bit 31 CCS_EXPECTED bit 30 READ_CEATA bit 27 DIS_BOOT bit 25 EXP_BOOT_ACK bit 24 BOOT_MODE bit 17 SDIO_PRDT bit 16 AUTO_CMD12 fld 15 14 RTRG { enum GE16 0; enum GE32 1; enum GE64 2; enum GE96 3 } fld 13 12 TTRG { enum LE16 0; enum LE32 1; enum LE64 2; enum LE96 3 } bit 11 IO_ABORT fld 10 9 BUS_WIDTH { enum 1BIT 0; enum 4BIT 2; enum 8BIT 3; } bit 7 INIT bit 6 BUSY bit 5 STREAM_BLOCK bit 4 WRITE_READ bit 3 DATA_EN fld 2 0 RESP_FMT } reg IMASK 0x24 { bit 31 DMA_DATA_DONE fld 28 24 PINS bit 23 WR_ALL_DONE bit 20 BCE bit 19 BDE bit 18 BAE bit 17 BAR bit 16 DMAEND bit 15 AUTO_CMD12_DONE bit 14 DATA_FIFO_FULL bit 13 DATA_FIFO_EMPTY bit 12 CRC_RES_ERROR bit 11 CRC_READ_ERROR bit 10 CRC_WRITE_ERROR bit 9 TIME_OUT_RES bit 8 TIME_OUT_READ bit 7 SDIO bit 6 TXFIFO_WR_REQ bit 5 RXFIFO_RD_REQ bit 2 END_CMD_RES bit 1 PROG_DONE bit 0 DATA_TRAN_DONE } reg IFLAG 0x28 { bit 31 DMA_DATA_DONE fld 28 24 PINS bit 23 WR_ALL_DONE bit 20 BCE bit 19 BDE bit 18 BAE bit 17 BAR bit 16 DMAEND bit 15 AUTO_CMD12_DONE bit 14 DATA_FIFO_FULL bit 13 DATA_FIFO_EMPTY bit 12 CRC_RES_ERROR bit 11 CRC_READ_ERROR bit 10 CRC_WRITE_ERROR bit 9 TIME_OUT_RES bit 8 TIME_OUT_READ bit 7 SDIO bit 6 TXFIFO_WR_REQ bit 5 RXFIFO_RD_REQ bit 2 END_CMD_RES bit 1 PROG_DONE bit 0 DATA_TRAN_DONE } reg LPM 0x40 { fld 31 30 DRV_SEL { enum FALL_EDGE 0 enum RISE_EDGE_DELAY_1NS 1 enum RISE_EDGE_DELAY_QTR_PHASE 2 } fld 29 28 SMP_SEL { enum RISE_EDGE 0 enum RISE_EDGE_DELAYED 1 } bit 0 ENABLE } reg DMAC 0x44 { bit 7 MODE_SEL fld 6 5 ADDR_OFFSET bit 4 ALIGN_EN fld 3 2 INCR bit 1 DMASEL bit 0 ENABLE } reg CTRL2 0x58 { fld 28 24 PIN_INT_POLARITY bit 4 STPRM fld 2 0 SPEED { enum DEFAULT 0 enum HIGHSPEED 1 enum SDR12 2 enum SDR25 3 enum SDR50 4 } } reg CLKRT 0x08 reg RESTO 0x10 reg RDTO 0x14 reg BLKLEN 0x18 reg NOB 0x1c reg SNOB 0x20 reg CMD 0x2c reg ARG 0x30 reg RES 0x34 reg RXFIFO 0x38 reg TXFIFO 0x3c reg DMANDA 0x48 reg DMADA 0x4c reg DMALEN 0x50 reg DMACMD 0x54 reg RTCNT 0x5c }