- Move all devkitpro includes before the Rockbox ones so that the macros which are both conflicting and unused can be undef'd
- Remove unused result variables
- Exclude an unused function from being compiled for this target
- Fix hex number formatting
- Fix the return value of dummy functions
- Fix macro redefinition in the plugins keypad config
- Remove duplicate button mapping
- Turn off -Wchar-subscripts as it's already handled in Rockbox's ctype.h
Change-Id: I3f5a3d492c585f233277a380feaea5fe877a044f
Confirmed on iFlash-modded ipodvideo, USB mass storage connections
frequently fail with bus resets during mount on macOS, and trigger
"reset high-speed USB device" errors on Linux during sequential
reads.
The root cause is: storage_read_sectors() calls yield() via
ata_wait_intrq(), which switches to the main thread running
handle_usb_events() loop. This calls send_event(GUI_EVENT_ACTIONUPDATE),
triggering LCD redraw that takes approximately 110ms. This stalls the
ATA DMA completion, causing the USB bulk transfer to time out from the
host's perspective.
This commit removes the yield to prevent the reading thread from being
preempted by the lengthy LCD redraw during DMA completion.
This also improves sequential read throughput from ~13MB/s to ~18MB/s.
Change-Id: Ia552f97aa0169c93c4f21e250d13dc3a626661d4
Move the rather large block of code that's been copied
in three separate linker scripts into the CPU header.
Change-Id: I9f38e4901fa4ff699f00d97064a9cdaf7cfd6aab
Move the definition of NOCACHE_BASE to the CPU headers
instead of having them copy-and-pasted in a few places.
Change-Id: Ibbab27a5a07906d46dbd4dd9065f2238bc885d6b
Mostly motivated by PP needing CACHEALIGN_SIZE in linker
scripts, which can't include system.h, so move these to
cpu.h instead. Also gets rid of the default 32 byte line
size that was used if the target didn't define alignment
itself. RK24xx, DM320, and JZ4740 were missing this but
have been confirmed (from datasheets) to use 32-byte cache
lines.
Add checks to make sure the macros are appropriately
(un)defined based on the HAVE_CPU_CACHE_ALIGN define,
and make sure their values are consistent when they
are defined.
Disable HAVE_CPU_CACHE_ALIGN for hosted targets since it
arguably doesn't matter if there's a cache, if we aren't
responsible for cache maintenance.
A few files in rbcodec use CACHEALIGN_SIZE, but these
can be converted to MEM_ALIGN_SIZE, which is identical
to CACHEALIGN_SIZE if the latter is defined. On other
targets, it aligns to at least sizeof(intptr_t).
Change-Id: If8cf8f6ec327dc3732f4cd5022a858546b9e63d6
The JZ47xx and S5L87xx processor families used their own
special defines (__ASSEMBLY__ and ASM respectively) in
their CPU headers to check if they were included from an
assembly source file.
For GCC the standard seems to be __ASSEMBLER__, so check
for that instead and remove the non-standard symbols.
Being more consistent across platforms makes it easier to
include cpu.h from cross-platform files (eg. plugin.lds).
Change-Id: I282930cad34e1a2ff18166f3b4338548b34f4a49
According to the datasheet, the PLL fractional mode is
apparently not supported in the medium VCO range.
The LCD isn't picky about front/back porch settings so
modify these to get a dot clock close to 6 MHz (within
~0.1% error).
Change-Id: I51647534db8c2b261391864db9262a0b04548e6d
Playback is implemented using a target-specific PCM layer,
using the STM32H7 SAI & DMA registers directly. There are
a number of pop/click issues:
1. Slight click when powering up the amplifiers
2. Click when starting and stopping playback
3. Popping when changing playback frequency
4. Popping when shutting down
It should be possible to eliminate or at least mitigate
(2) to (4) in software, but (1) happens as a result of
powering on the amplifiers while everything is muted so
might be unavoidable.
Change-Id: I398b66596176fb2341beb7deba7bf6f4f3fb82b3
move target-specific pcm operations into builtin_pcm_sink.
in subsequent commits, another pcm_sink is added, and it becomes
possible to switch between them.
Change-Id: I8f8b9661e01d6e6472f34224ddc3760856778457
Though the rev1 hardware is capable of recording from a
headset mic, this feature seems likely to be dropped on
future hardware revisions, and I don't see much point to
implementing it now.
Change-Id: I77e403bdd1ca53f9018835d3c3042dc86ee0f8f3
According to RM0433 the DCTRL register needs to be written
after DLENR and DTIMER. This is respected for data transfer
commands but not for non-data commands. Nothing bad seems
to be happening because of this, but it seems wise to rectify
the issue.
Change-Id: I55d8f2c1994bff747e5978847fda57445f001b02
According to RM0433 consecutive writes to the CLKCR and CMDR
registers must be separated by at least 7 AHB clock cycles.
The initialization code didn't respect this and it seemed to
be causing a nasty bug, where the SDMMC bus clock got stuck
at 400 KHz in hardware. Despite the CLKCR register reading
back the correct value, it could not be written with a new
value even in the debugger; resetting the peripheral was the
only way out of this state.
Adding some dummy register reads after any access to CLKCR
should insert the necessary number of wait states. Without
the fix, the SDMMC clock gets stuck about 12% of the time.
With this fix, the clock always initializes correctly.
Change-Id: Iba85b8e1e3c60992ddc42fb4c1e66c37941ed617
Replace the factor calculation from pcm-alsa.c, which
is based on signal *power* ratios, with the fp_factor()
calculation that is based on amplitude ratios. Because
power changes with the square of amplitude, this means
1 dB of power equals 2 dB of amplitude.
Rockbox's volume controls are amplitude-based, so the
smallest step size for pcm-alsa was effectively 2 dB.
The fp_factor() method supports 0.1 dB steps and is a
bit more accurate besides, so it's simply superior in
all respects (aside from taking a few more CPU cycles
to calculate the factor).
Change-Id: I34d143c225d8b5e085cde299fc405f83c13314bf
Disabling an IRQ in the NVIC may not take effect right away;
if the IRQ is being disabled to implement a critical section
it's necessary to follow up with dsb + isb to serialize the
NVIC update. Add a helper function for doing this.
Change-Id: Iaaa238ad39997cc3c6d62867d265cf9e9e0e5c4b
At low speed there's some occasional corrupted pixels,
most visible on album art and such; this goes away at
medium speed.
Change-Id: Ice4eaec4284023d2d3f5c571b242cb27ebc26da9
The problem with drive strength and things not working reliably
at 50 MHz turned out to be entirely caused by the ESD diodes on
the data/command/clock lines, which have a whopping 200-300 pF
junction capacitance -- 6-10x higher than the 30 pF limit given
by the MMC spec.
After desoldering the diodes the bus seems stable at 50 MHz and
with any drive strength (note MEDIUM is still fast enough even
for 50 MHz, so the drive strength is unchanged).
Change-Id: If9847ee4145f5ed2f7e172cfa89acad0737a897f
* Get rid of the SD_CIM_RESET meta-command and put all
reset/init logic into one place
* Don't double-issue the SD_GO_IDLE_STATE command
* Explicitly set lowest speed upon reset
Change-Id: I5abfe9f64997e39087b8a77d525f90c77733a1a8
* Rework logf/DEBUG distinction
* Don't try to init a card that isn't detected
* Inform card that host supports SDUC
* Implement CMD22 (SET_UPPER_ADDR)
* Implement CMD23 (SET_BLOCK_COUNT)
* Disable DMA for transfers under 512 bytes
* Created ACMD+data xfer command path
* Incorrect handling of RESPONSE_R7
* Clean up 4bit stuff, only turn it on after we enable it in the card.
* Clear END_CMD_RES bit _after_ we check the status
* Probe SCR <-- NOT YET WORKING, DISABLED
jz4740 had these additional improvements:
* Restructuring to bring it closer to 4760 driver
* Unified read/write setup code
* IRQ handling and polling improvements
Change-Id: I47379f097af4bf50177499b3d80a6c9c42d48057
Low speed works for 50pF loads up to 12 MHz. LCD signals
fall well within those limits so there's no reason to use
any higher speed.
Change-Id: I6dab899fac316bb02572174ef13a98cccbf4ae66
The semaphore was released after all bytes were read/written
without waiting for the EOT event, which is why the delay at
the end of the transfer needed to be longer than expected.
Change-Id: I6b48fc01cda69564c0ec8f843afd1b0c3a9c5a3c
I have a 1TB SD card that gets filesystem corruption when writing large
amounts of data when using Rockbox in USB storage mode. The card doesn't show
this behaviour when using the original firmware or when using an external SD
card writer.
This is on an Aigo Eros Q device. Same brand 512GB card does not exhibit this
behaviour.
Whether this specific SD card explicitly requires CMD23 or if there's a
problem with the controller's timing of auto-CMD12 in combination with this
card is currently unknown, but implementing it does solve the problem.
This change request implements CMD23 by first probing if SBC is supported by
the SD card and then using it instead of AUTO_CMD12.
Change-Id: Ib2dc8e179b0fab98ca59c348061cb7d5850884dd
The driver didn't handle the busy signal at the end of
some command responses (R1b response type), notably the
CMD12 (STOP_TRANSMISSION) sent after a multiblock write
would time out because DTIMER==0 and leave the DPSM in
an incorrect state for the next command, causing a hang.
Change-Id: I406337a7612f759418a4872979aa2de5aa2244c7
When doing I/O, the interrupt can rarely fire with no
active command and no status bits set. This is probably
because the interrupt is set pending by the NVIC while
the handler is already running, so should be harmless.
Change-Id: I0c2570abe6e3c85ddbfa2ebe0afcf8677b77408f
They haven't seen development activity for the better part
of two decades and apparently were never able to even boot
to Rockbox, although the Rockbox bootloader could load the
original firmware.
Change-Id: I5cfa5909c21feaf2825aa685a05e78044b893a13
Allow toggling the system debug state from the debug menu
in Rockbox, or by holding a button combo at boot, so that
an SWD/JTAG debugger can be attached to normal non-debug
builds without too much hassle.
Change-Id: Iee47ef916ade2e5ec1094a63c68e48f1b27b0bbb
While 50 MHz works for low activity and small amounts of
data, there are frequent CRC errors when handling larger
transfers. Increasing drive strength only makes it worse.
Everything seems stable at 25 MHz though.
Change-Id: I3471c490ab63b2302b21ee2fe601519ee5a40ce5
Both targets were part of the (presumably dead) Lyre project
and no longer build. The Mini2440 was much more complete than
the Lyre and doesn't seem terribly difficult to fix up to the
point where it at least builds, if someone still cares -- but
given it is a dev board in a box, it's unlikely it ever saw
much use.
Change-Id: I09745379d28db69ea9aaf77f0a62b049884260e1
Some purely mechanical fixes to get the normal build
working. Besides missing symbols all the plugins and
codecs build just fine.
Change-Id: I946ba39096a46be8308450bafd51a0995db8e323
It doesn't seem to have been functional ever and currently
doesn't build; eg. the last commit to the LCD driver added
a syntax error, and there's some duplicate functions between
mmu-armv6.S and system-pp502x.c. Doesn't seem worth the
effort to fix.
Change-Id: I82b5bec3ed9686f28aedbe283818af792b96daf4
These targets haven't seen any changes since 2008-09
have bitrotted to the point they don't compile anymore.
With only internal NAND flash for storage which doesn't
seem to have ever been accessible from Rockbox, they've
never been usable and there's probably not much point
keeping them around any more.
Change-Id: I2fc63da20682b439126672065ae013044cb2d1c4
It looks like the GDB stub only ever worked for the Archos
Recorder and iRiver IFP-7xx, neither of which are in-tree
any more.
Change-Id: If1910675b88b4707d26df9bc095818902af2d25b
The section copy loops in crt0.S rely on sections starting
and ending on 4-byte aligned addresses. If the last variable
alloacted in the BSS section isn't a multiple of 4 bytes,
then _bssend can get misaligned and break the copy loop.
This problem was masked by -fcommon since COMMON variables
go at the end of the BSS section, and they were for the most
part a multiple of 4 bytes. The switch to -fno-common broke
the bootloader because with COMMON gone, the last thing in
BSS was a 1-byte variable in led.o. The main binary appears
to have had the correct alignments by sheer luck.
Change-Id: I21ee3653d89d1607a2f458c457f1a51e33c22f05
We were using a definition of 0b100 for "Quad Input / Quad Output" mode
which is marked as "reserved" in the X1000 TRM. The correct value is
0b101.
Somehow this "worked" for some devices but failed for others?
Credit for this discovery+fix goes to forum user ZappBranigan2972
Change-Id: Iedbd2d1b6da55113e266ad8aa51fc9c3130bf2b8
Using a simple memcpy to a separate framebuffer prevents
objectionable levels of flickering caused by scanning out
the main framebuffer while it's modified between updates.
With optimized memcpy, copying the whole framebuffer takes
about 260us at maximum CPU+bus frequency. Using DMA would
likely be a bit faster and more power-efficient, but that
can be left as a future optimization.
Change-Id: Ia6dc36d797cdb7a5f6663078c0ecce661267bedf
Either QSPI is not wired up, or there is some other issue preventing
them from working correctly.
If this doesn't show any more issues then we should be able to produce a
new set of bootloader builds enabling support for the HifiWalker H2 v2.3
variant. We will eventually find out if other OEMs have chosen dfferent
flash parts for their specific ErosQ/K variations.
(Credit for these experiments goes to the forum users
ZappBranigan2972 and gonzyfrigus)
Change-Id: I349f4bbac509010753ac2ad24ad42a234cccdea5
