Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.
Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
only check button values with adc when buttons are actually pressed
battery level check frequency is now around 30 seconds
switched to polling for the battery voltage w/ timeout
Ifdef functions Allow BACK OPTION PLAY to be the first of a two key combo
Change-Id: Icb48d62ac8d82b4dc931df5e1c5b4a84a9a69772
Back off to 480MHz [max] clock, bus/mem clock of 120MHz.
576 is unstable on at least one unit, and 528 still glitches.
Change-Id: I020e48532524e739f3bfa42bed570381ccd34959
* Don't stop clock before switching speeds
* Don't stop clock prior to transactions
* Stop clock at the end of transactions
Will result in slightly better performance and some power saving when
we're not actively using the SD peripheral.
Change-Id: I1c82476cad97137b1469900645ecf7bb0887119a
* Check to see if clock is [not] running prior to [en|dis]abling it
* Stop clock _prior_ to resetting controller
* Stop clock after transaction is completed, not before initiating it
* Use controller's low power mode (disables clocks when idle)
* Fix, and enable, interrupt-driven DMA transfers
* Fixes for full interrupt-driven operation (WIP, still broken)
Change-Id: I723ffa6450fc85f97898c8a8b3e538ae31c4858e
There's a code path that calls sd_init_device() while we hold sd_mtx, but
sd_init_device() tries to obtain the mutex while doing its work.
Change-Id: I882c595e9e7cd2224b1db0d413925668628476e9
* Allows both SD interfaces to have requests in flight simultaneously
* Fixed a deadlock in the hotswap code
* Ensure TX DMA is idle before initiating a request (bug due to a typo)
Change-Id: I988fa29df5f8e41fc6bbdcc517db89842003b34d
(More specifically, use the SoC's "OS Timer", slaved to the main XTAL so
it doesn't matter how the main CPU is clocked)
Change-Id: I799561ac823ff7f659a05144cf03b6a13d57ea7b
PLL1 clock for those frequencies has been dropped from 508 to 169.5 MHz,
so it's still a respectable reduction.
(I'm not sure how/why it ever worked with the XTAL source, but it did,
and was off by an audible amount)
Change-Id: I614d87e7dfdfe9210702b9c646d3863c06d6780b
* for <= 48KHz, BCLK must be 256*freq (ie bdiv = 4)
* for <= 96KHz, BCLK must be 128*freq (ie bdiv = 2)
* for 11/22/44/88 KHz, disable PLL1 and run off XTAL
* cut PLL1 with 12/24/48/98 KHz audio from 516->86MHz
* cut PLL1 with 8/16/32/64 KHz audio from 426->106.5MHz
This should result in significant power savings for
common 44.1KHz audio playback, and pretty good savings
for everything else.
As an added bonus:
* enable de-emphasis filters at 32, 44.1, and 48 KHz
Change-Id: Ie59067cd46c47e62abf4a32c53519efad104d6c8
default/low speed is 192 MHz, Max is 576
Downclock PCLK/MCLK/etc to 96MHz to save a bit of juice
Honestly the high speed could be dialed down to, eg 384
as this thing is so bloody fast..
Change-Id: Ie65597c74290f1603e65f69dae8e75b59c8ba0b4
PLL0 Needs to be a multiple of 48MHz for sane USB operation!
(Indeed, "typical" clock for this part is 528, but that seems a
waste of power)
Also fixes a minor bugaboo in the jz4670 usb divisor calculation
that won't matter until we enable reclocking
Change-Id: I40b1fd1ae48871e50885981ccc8b01feb711b9a5
Note: I left behind lcd_bitmap in features.txt, because removing it
would require considerable work in the manual and the translations.
Change-Id: Ia8ca7761f610d9332a0d22a7d189775fb15ec88a
Main/IRQ from: 7.5/0.75 to: 7.25/1.0
With the reduction of the opus codec stack usage, giving the IRQ stack
some additional breathing room is now possible.
Change-Id: Id0cd3747fcaab70e2360667ac8c1a97ba7234ccf
This greatly increases the stability of SD card write operations.
(I suspect the underlying problem is not IRQ operation itself, instead
being exacerbated by it..)
Change-Id: Ia00f0656abd4b3cb0b1b5fc9db7c1b6a02847956
This allows targets to automatically switch audio settings when the
line out is plugged/unplugged.
Only hooked up on the xDuoo X3, but there are other potential users.
Change-Id: Ic46a329bc955cca2e2ad0335ca16295eab24ad59
New amounts:
7.50K main stack
0.75K irq stack
Prior values of 8K+1K overflowed IRAM by ~660 bytes on Onda 7x7 targets,
but worked on the xDuoo X3.
(The discrepancy is due to the Onda targets having more LCD code shoved
into IRAM.)
Change-Id: I16fcfae3c5f3e36db688dfa9167b620584e79df8
