For some reason 4 bit widebus is creating issues when writing to the .rockbox directory so revert 4 bit widebus and the revision to the write delay that was added as a fix.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24054 a1c6a512-1295-4272-9138-f99709370657
Making this delay apply to all non-HS SD cards seems to fix some data corruption issues that came up with the switch to 4-bit widebus.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24019 a1c6a512-1295-4272-9138-f99709370657
MCI_RESPONSE_ERROR covers MCI_CMD_TIMEOUT & MCI_CMD_CRC_FAIL and makes it more clear that these are errors in the response and not the command itself.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24003 a1c6a512-1295-4272-9138-f99709370657
Both the internal and uSD cards are now put into 4 bit widebus mode during initialization except for bootloader.
Add MCI_START_BIT_ERR to MCI_ERROR list and change name to MCI_DATA_ERROR for clarity.
Make appropriate changes to SD error codes.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23977 a1c6a512-1295-4272-9138-f99709370657
This patch changes all references/assumptions of PCLK to IDE_CLK for the internal pl180 controller.
Lower the AS3525_IDE_FREQ to 50 MHz in order to be able to divide by 2 for 25 MHz on the internal SD card.
Adjust the code in debug-as3525.c to account for the change and the frequencies reported should be correct.
Add some #if defined(HAVE_MULTIDRIVE) conditionals to cut out the code dealing with uSD for the clip.
Isolate the write delay needed for low frequency writes to only run for standard speed uSD cards. That is the only case for an MCICLK at 15.5 MHz.
Internal cards run at 25 MHz, HS uSD at 31 MHz, and standard speed uSD cards at 15.5 MHz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23929 a1c6a512-1295-4272-9138-f99709370657
Some cards need this delay now that we're running at ident speed during this part of the init stage.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23919 a1c6a512-1295-4272-9138-f99709370657
Addition of a small write delay avoids data crc failures at lower MCICLK frequencies.
Check the actual speed value from the card's CSD register to determine HS status. HS cards can run at twice the speed of standard speed SD cards.
Internal cards & standard speed uSD now run at PCLK/4 = 15.5 MHz. HS uSD cards run at PCLK/2 = 31 MHz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23901 a1c6a512-1295-4272-9138-f99709370657
It seems that lowering the operating frequency for the SD cards has made some uSD cards have problems with the init process.
By moving the boost from ident to operating frequency to after the switch to HS timing these card now seem to init normally.
We still need to fix the problem where the internal cards and non HS uSD cards are still slightly overclocked at 31 MHz.
As of now we experience data crc failures during writes at the next lower frequency of 15.5 MHz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23870 a1c6a512-1295-4272-9138-f99709370657
This is within the SD Spec for v2 High Speed cards but still over the 25 MHz limit for v1 and non-HS v2 cards.
Test_disk write & verify passes on both internal and uSD.
The v1 cards still need to be lowered to 15 MHz but that causes data crc failures at this point.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23835 a1c6a512-1295-4272-9138-f99709370657
Currently the bypass bit is not cleared so it's possible to enter the identification phase at bypass speed instead of ident speed.
The simplest solution to ensure the bypass bit is not set is to set the register with an = operation instead of |=.
This makes setting the MCI_CLOCK register at the end of the controller init unnecessary.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23830 a1c6a512-1295-4272-9138-f99709370657
If the controllers were already enabled there was a chance we could try to read the MCI_CLOCK registers while the cards were buffering and then disable the controllers prematurely.
I guess funman knows and sees all!! Thanks funman.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23811 a1c6a512-1295-4272-9138-f99709370657
Enabling/disabling of the NAF and IDE clocks is now grouped together as both are related to the internal SD.
Sequence for disabling SD now mirrors the enable sequence.
Comments added to make it easier to follow the configuration change for XPD from gpio to mci-sd and back.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23808 a1c6a512-1295-4272-9138-f99709370657
We had 3 different references to the same value. Rockbox always uses a blocksize of 512 bytes for SD and we were using SECTOR_SIZE, SD_BLOCK_SIZE, & card_info[drive].blocksize to use this value. Now the only reference being used is SD_BLOCK_SIZE.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23746 a1c6a512-1295-4272-9138-f99709370657
When read it returns all enabled interrupt sources
When written it enables interrupt sources for each bit set
So just like VIC_INT_EN_CLEAR, we don't have to read the previous value
before writing to it (VIC_INT_EN_CLEAR is write-only anyway)
Thanks to Fred Bauer for spotting
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23734 a1c6a512-1295-4272-9138-f99709370657
We don't need to check the FIFO for MCI_RX_ACTIVE because we don't experience problems reading from the SD cards.
We need the MCI_TX_ACTIVE FIFO check during writes because some SD cards spend longer times in the PRG state
programming the data that has been written to them.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23733 a1c6a512-1295-4272-9138-f99709370657
We use wait_for_state() before any command that requires a state prior to being sent. Waiting after a transfer is not needed.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23732 a1c6a512-1295-4272-9138-f99709370657
The crc check on responses to sd commands was being bypassed due to a SD_APP_OP_COND special case. Now a short response is returned
even if the crc check fails so we can check the busy bit. The send_cmd() function still returns a false value but it loads the response
variable with the cmd response.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23718 a1c6a512-1295-4272-9138-f99709370657
- two essential parts of Sansa AMS drivers are optimzed away in newer gcc, so mark them volatile.
- use "r" instead of "i" (which is apparently invalid syntax) for the input list in some inline assembly
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23634 a1c6a512-1295-4272-9138-f99709370657
Adjust SD timeouts accordingly.
Adjust code in debug-as3525.c to display correct frequencies on system/debug/View disk info page.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23350 a1c6a512-1295-4272-9138-f99709370657
Internal cards are v1 sd cards so no need to include this code for the clip.
Move transition from STBY -> TRAN-> STBY states inside the if(sd_v2) conditional check for HS switch as it's not needed for non HS cards.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23331 a1c6a512-1295-4272-9138-f99709370657
If a card is reinitialized now the ident frequency is used instead of the bypass frequency during the identification phase.
Added comments throughout sd_init_card() to help follow init process and highlight indent stage.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23256 a1c6a512-1295-4272-9138-f99709370657
Reimplement voltage scaling on AMS Sansas at 1.10v during unboosted operation to improve runtimes. The voltage is now also boosted during disk access if a µSD is present. This prevents the µSD problems we saw on the last implementation.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23193 a1c6a512-1295-4272-9138-f99709370657
Remove useless E200V2 || FUZE || C200V2 : all those models have
MULTIDRIVE and/or HOTSWAP defined and have no specific difference.
Correct some comments
Remove HAVE_MULTIDRIVE within HAVE_HOTSWAP since HOTSWAP imply MULTIDRIVE
Change HOTSWAP to MULTIDRIVE where needed
Use NUM_DRIVES in sd_num_drives()
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23180 a1c6a512-1295-4272-9138-f99709370657
We are unable to successfully put the pl180 controller into 4 bit mode so we should not put the cards into widebus mode for now.
The blocklength is hardcoded to 512 in sd.c and BLOCKLEN defaults to 512 so this command is not needed.
It appears the internal SD card is not HS capable but sending it the HS switch command does not seem to hinder it's init process.
Assume all SD_V2 cards are HS capable and send them the HS switch command.
If View disk info shows 50.0 MBit/s the card has HS timings.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23137 a1c6a512-1295-4272-9138-f99709370657
This still doesn't solve the problem of the cards being overclocked at 62MHz but we can mitigate this a bit by switching to HS timings.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23088 a1c6a512-1295-4272-9138-f99709370657
Nothing should change, since the value of transfer didn't change in the == case, but it saves executing this case at least.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21931 a1c6a512-1295-4272-9138-f99709370657
The maximum number of errors is 10 (arbitrary)
A recovery mechanism is not in place (yet) but could be implemented in the future
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21776 a1c6a512-1295-4272-9138-f99709370657
clocks disabling and mutex unlocking were not made in case of errors
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21773 a1c6a512-1295-4272-9138-f99709370657
