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as3525v2: assume plla is the source for pclk (verified with timer frequency)

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The frequencies are correctly displayed in the debug menu

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25418 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2010-04-01 06:05:24 +00:00
parent a28a9210d0
commit fa59c7b686
2 changed files with 12 additions and 3 deletions
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6
firmware/target/arm/as3525/clock-target.h
View file

@ -70,7 +70,11 @@
#define AS3525_FCLK_FREQ AS3525_PLLA_FREQ
/* XXX: CGU_PERI might also be different (i.e. no PCLK_DIV1_SEL), but if we use
* the same frequency for DRAM & PCLK it's not a problem as the bit is unset */
* the same frequency for DRAM & PCLK it's not a problem as the bit is unset
*
* Note that setting bits 1:0 have no effect and they always read back as 0
* Perhaps it means CGU_PERI defaults to PLLA as source ?
*/
#define AS3525_DRAM_FREQ 60000000 /* Initial DRAM frequency */
#define AS3525_PCLK_FREQ AS3525_DRAM_FREQ/1

9
firmware/target/arm/as3525/debug-as3525.c
View file

@ -143,7 +143,13 @@ static int calc_freq(int clk)
return 0;
}
case CLK_EXTMEM:
/* bits 1:0 of CGU_PERI always read as 0 and we assume source = PLLA */
#if CONFIG_CPU == AS3525
switch(CGU_PERI & 3) {
#else
/* bits 1:0 of CGU_PERI always read as 0 and we assume source = PLLA */
switch(1) {
#endif
case 0:
return CLK_MAIN/(((CGU_PERI>>2)& 0xf)+1);
case 1:
@ -151,9 +157,8 @@ static int calc_freq(int clk)
case 2:
return calc_freq(CLK_PLLB)/(((CGU_PERI>>2)& 0xf)+1);
case 3:
return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1);
default:
return 0;
return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1);
}
case CLK_PCLK:
return calc_freq(CLK_EXTMEM)/(((CGU_PERI>>6)& 0x1)+1);