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imx233: normalise clkctrl

Browse source 
The clkctrl functions were becoming a mess. Normalise the names,
get rid of the xtal derived as special case and use the same
interface.

Change-Id: Ib954a8d30a6bd691914b5e0d97774ec9fc560c50
This commit is contained in:
Amaury Pouly 2013-06-16 20:08:49 +02:00
parent 84fc327aeb
commit f5ac658d16
12 changed files with 154 additions and 245 deletions
Download patch file Download diff file Expand all files Collapse all files

4
firmware/target/arm/imx233/audioout-imx233.c
View file

@ -40,7 +40,7 @@ void imx233_audioout_preinit(void)
/* Enable AUDIOOUT block */
imx233_reset_block(&HW_AUDIOOUT_CTRL);
/* Enable digital filter clock */
imx233_clkctrl_enable_xtal(XTAL_FILT, true);
imx233_clkctrl_enable(CLK_FILT, true);
/* Enable DAC */
BF_CLR(AUDIOOUT_ANACLKCTRL, CLKGATE);
/* Set capless mode */
@ -97,7 +97,7 @@ void imx233_audioout_close(void)
/* Gate off DAC */
BF_SET(AUDIOOUT_ANACLKCTRL, CLKGATE);
/* Disable digital filter clock */
imx233_clkctrl_enable_xtal(XTAL_FILT, false);
imx233_clkctrl_enable(CLK_FILT, false);
/* will also gate off the module */
BF_CLR(AUDIOOUT_CTRL, RUN);
}

151
firmware/target/arm/imx233/clkctrl-imx233.c
View file

@ -20,29 +20,19 @@
****************************************************************************/
#include "clkctrl-imx233.h"
#define __CLK_CLKGATE (1 << 31)
#define __CLK_BUSY (1 << 29)
void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable)
{
if(enable)
HW_CLKCTRL_XTAL_CLR = xtal_clk;
else
HW_CLKCTRL_XTAL_SET = xtal_clk;
}
bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk)
{
return HW_CLKCTRL_XTAL & clk;
}
void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable)
void imx233_clkctrl_enable(enum imx233_clock_t clk, bool enable)
{
/* NOTE some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */
bool gate = !enable;
switch(clk)
{
case CLK_PIX: BF_WR(CLKCTRL_PIX, CLKGATE, gate); break;
case CLK_SSP: BF_WR(CLKCTRL_SSP, CLKGATE, gate); break;
case CLK_DRI: BF_WR(CLKCTRL_XTAL, DRI_CLK24M_GATE, gate); break;
case CLK_PWM: BF_WR(CLKCTRL_XTAL, PWM_CLK24M_GATE, gate); break;
case CLK_UART: BF_WR(CLKCTRL_XTAL, UART_CLK_GATE, gate); break;
case CLK_FILT: BF_WR(CLKCTRL_XTAL, FILT_CLK24M_GATE, gate); break;
case CLK_TIMROT: BF_WR(CLKCTRL_XTAL, TIMROT_CLK32K_GATE, gate); break;
case CLK_PLL:
/* pll is a special case */
if(enable)
@ -58,18 +48,23 @@ void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable)
}
}
bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t clk)
bool imx233_clkctrl_is_enabled(enum imx233_clock_t clk)
{
switch(clk)
{
case CLK_PLL: return BF_RD(CLKCTRL_PLLCTRL0, POWER);
case CLK_PIX: return !BF_RD(CLKCTRL_PIX, CLKGATE);
case CLK_SSP: return !BF_RD(CLKCTRL_SSP, CLKGATE);
case CLK_DRI: return !BF_RD(CLKCTRL_XTAL, DRI_CLK24M_GATE);
case CLK_PWM: return !BF_RD(CLKCTRL_XTAL, PWM_CLK24M_GATE);
case CLK_UART: return !BF_RD(CLKCTRL_XTAL, UART_CLK_GATE);
case CLK_FILT: return !BF_RD(CLKCTRL_XTAL, FILT_CLK24M_GATE);
case CLK_TIMROT: return !BF_RD(CLKCTRL_XTAL, TIMROT_CLK32K_GATE);
default: return true;
}
}
void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div)
void imx233_clkctrl_set_div(enum imx233_clock_t clk, int div)
{
/* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant !
* assume that we always derive emi and cpu from ref_XX */
@ -85,7 +80,7 @@ void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div)
}
}
int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk)
int imx233_clkctrl_get_div(enum imx233_clock_t clk)
{
switch(clk)
{
@ -99,7 +94,7 @@ int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk)
}
}
void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
void imx233_clkctrl_set_frac_div(enum imx233_clock_t clk, int fracdiv)
{
#define handle_frac(dev) \
case CLK_##dev: \
@ -120,7 +115,7 @@ void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
#undef handle_frac
}
int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk)
int imx233_clkctrl_get_frac_div(enum imx233_clock_t clk)
{
#define handle_frac(dev) \
case CLK_##dev:\
@ -139,7 +134,7 @@ int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk)
#undef handle_frac
}
void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
void imx233_clkctrl_set_bypass(enum imx233_clock_t clk, bool bypass)
{
uint32_t msk;
switch(clk)
@ -157,7 +152,7 @@ void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
HW_CLKCTRL_CLKSEQ_CLR = msk;
}
bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk)
bool imx233_clkctrl_get_bypass(enum imx233_clock_t clk)
{
switch(clk)
{
@ -169,7 +164,7 @@ bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk)
}
}
void imx233_clkctrl_enable_usb_pll(bool enable)
void imx233_clkctrl_enable_usb(bool enable)
{
if(enable)
BF_SET(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
@ -177,12 +172,12 @@ void imx233_clkctrl_enable_usb_pll(bool enable)
BF_CLR(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
}
bool imx233_clkctrl_is_usb_pll_enabled(void)
bool imx233_clkctrl_is_usb_enabled(void)
{
return BF_RD(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
}
void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div)
void imx233_clkctrl_set_auto_slow_div(unsigned div)
{
/* the SLOW_DIV must only be set when auto-slow is disabled */
bool old_status = imx233_clkctrl_is_auto_slow_enabled();
@ -191,7 +186,7 @@ void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div)
imx233_clkctrl_enable_auto_slow(old_status);
}
enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void)
unsigned imx233_clkctrl_get_auto_slow_div(void)
{
return BF_RD(CLKCTRL_HBUS, SLOW_DIV);
}
@ -206,30 +201,12 @@ bool imx233_clkctrl_is_auto_slow_enabled(void)
return BF_RD(CLKCTRL_HBUS, AUTO_SLOW_MODE);
}
void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable)
{
if(enable)
HW_CLKCTRL_HBUS_SET = monitor;
else
HW_CLKCTRL_HBUS_CLR = monitor;
}
bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor)
{
return HW_CLKCTRL_HBUS & monitor;
}
bool imx233_clkctrl_is_emi_sync_enabled(void)
{
return BF_RD(CLKCTRL_EMI, SYNC_MODE_EN);
}
unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
unsigned imx233_clkctrl_get_freq(enum imx233_clock_t clk)
{
switch(clk)
{
case CLK_PLL: /* PLL: 480MHz when enable */
return imx233_clkctrl_is_clock_enabled(CLK_PLL) ? 480000 : 0;
return imx233_clkctrl_is_enabled(CLK_PLL) ? 480000 : 0;
case CLK_XTAL: /* crystal: 24MHz */
return 24000;
case CLK_CPU:
@ -238,78 +215,78 @@ unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
/* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider
* otherwise, clk_p derived from clk_cpu via int div and clk_cpu
* derived from clk_pll fracdiv */
if(imx233_clkctrl_get_bypass_pll(CLK_CPU))
if(imx233_clkctrl_get_bypass(CLK_CPU))
{
ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
ref = imx233_clkctrl_get_freq(CLK_XTAL);
/* Integer divide mode vs fractional divide mode */
if(BF_RD(CLKCTRL_CPU, DIV_XTAL_FRAC_EN))
return (ref * BF_RD(CLKCTRL_CPU, DIV_XTAL)) / 32;
else
return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
return ref / imx233_clkctrl_get_div(CLK_CPU);
}
else
{
ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
ref = imx233_clkctrl_get_freq(CLK_PLL);
/* fractional divider enable ? */
if(imx233_clkctrl_get_fractional_divisor(CLK_CPU) != 0)
ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_CPU);
return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
if(imx233_clkctrl_get_frac_div(CLK_CPU) != 0)
ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_CPU);
return ref / imx233_clkctrl_get_div(CLK_CPU);
}
}
case CLK_HBUS:
{
/* Derived from clk_p via integer/fractional div */
unsigned ref = imx233_clkctrl_get_clock_freq(CLK_CPU);
if(imx233_clkctrl_get_fractional_divisor(CLK_HBUS) != 0)
ref = (ref * imx233_clkctrl_get_fractional_divisor(CLK_HBUS)) / 32;
if(imx233_clkctrl_get_clock_divisor(CLK_HBUS) != 0)
ref /= imx233_clkctrl_get_clock_divisor(CLK_HBUS);
unsigned ref = imx233_clkctrl_get_freq(CLK_CPU);
if(imx233_clkctrl_get_frac_div(CLK_HBUS) != 0)
ref = (ref * imx233_clkctrl_get_frac_div(CLK_HBUS)) / 32;
if(imx233_clkctrl_get_div(CLK_HBUS) != 0)
ref /= imx233_clkctrl_get_div(CLK_HBUS);
return ref;
}
case CLK_IO:
{
/* Derived from clk_pll via fracdiv */
unsigned ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
if(imx233_clkctrl_get_fractional_divisor(CLK_IO) != 0)
ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_IO);
unsigned ref = imx233_clkctrl_get_freq(CLK_PLL);
if(imx233_clkctrl_get_frac_div(CLK_IO) != 0)
ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_IO);
return ref;
}
case CLK_PIX:
{
unsigned ref;
/* Derived from clk_pll or clk_xtal */
if(!imx233_clkctrl_is_clock_enabled(CLK_PIX))
if(!imx233_clkctrl_is_enabled(CLK_PIX))
ref = 0;
else if(imx233_clkctrl_get_bypass_pll(CLK_PIX))
ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
else if(imx233_clkctrl_get_bypass(CLK_PIX))
ref = imx233_clkctrl_get_freq(CLK_XTAL);
else
{
ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
if(imx233_clkctrl_get_fractional_divisor(CLK_PIX) != 0)
ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_PIX);
ref = imx233_clkctrl_get_freq(CLK_PLL);
if(imx233_clkctrl_get_frac_div(CLK_PIX) != 0)
ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_PIX);
}
return ref / imx233_clkctrl_get_clock_divisor(CLK_PIX);
return ref / imx233_clkctrl_get_div(CLK_PIX);
}
case CLK_SSP:
{
unsigned ref;
/* Derived from clk_pll or clk_xtal */
if(!imx233_clkctrl_is_clock_enabled(CLK_SSP))
if(!imx233_clkctrl_is_enabled(CLK_SSP))
ref = 0;
else if(imx233_clkctrl_get_bypass_pll(CLK_SSP))
ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
else if(imx233_clkctrl_get_bypass(CLK_SSP))
ref = imx233_clkctrl_get_freq(CLK_XTAL);
else
ref = imx233_clkctrl_get_clock_freq(CLK_IO);
return ref / imx233_clkctrl_get_clock_divisor(CLK_SSP);
ref = imx233_clkctrl_get_freq(CLK_IO);
return ref / imx233_clkctrl_get_div(CLK_SSP);
}
case CLK_EMI:
{
unsigned ref;
/* Derived from clk_pll or clk_xtal */
if(imx233_clkctrl_get_bypass_pll(CLK_EMI))
if(imx233_clkctrl_get_bypass(CLK_EMI))
{
ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
ref = imx233_clkctrl_get_freq(CLK_XTAL);
if(BF_RD(CLKCTRL_EMI, CLKGATE))
return 0;
else
@ -317,16 +294,24 @@ unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
}
else
{
ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
if(imx233_clkctrl_get_fractional_divisor(CLK_EMI) != 0)
ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_EMI);
return ref / imx233_clkctrl_get_clock_divisor(CLK_EMI);
ref = imx233_clkctrl_get_freq(CLK_PLL);
if(imx233_clkctrl_get_frac_div(CLK_EMI) != 0)
ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_EMI);
return ref / imx233_clkctrl_get_div(CLK_EMI);
}
}
case CLK_XBUS:
return imx233_clkctrl_get_clock_freq(CLK_XTAL) /
imx233_clkctrl_get_clock_divisor(CLK_XBUS);
return imx233_clkctrl_get_freq(CLK_XTAL) / imx233_clkctrl_get_div(CLK_XBUS);
default:
return 0;
}
}
void imx233_clkctrl_init(void)
{
/* set auto-slow monitor to all */
HW_CLKCTRL_HBUS_SET = BF_OR8(CLKCTRL_HBUS,
APBHDMA_AS_ENABLE(1), TRAFFIC_JAM_AS_ENABLE(1), TRAFFIC_AS_ENABLE(1),
APBXDMA_AS_ENABLE(1), CPU_INSTR_AS_ENABLE(1), CPU_DATA_AS_ENABLE(1),
DCP_AS_ENABLE(1), PXP_AS_ENABLE(1));
}

76
firmware/target/arm/imx233/clkctrl-imx233.h
View file

@ -50,67 +50,33 @@ enum imx233_clock_t
CLK_XTAL, /* freq */
CLK_EMI, /* freq, div, frac, bypass */
CLK_XBUS, /* freq, div */
CLK_FILT, /* enable */
CLK_DRI, /* enable */
CLK_PWM, /* enable */
CLK_TIMROT, /* enable */
CLK_UART, /* enable */
};
enum imx233_xtal_clk_t
{
XTAL_FILT = 1 << 30,
XTAL_DRI = 1 << 28,
XTAL_TIMROT = 1 << 26,
XTAM_PWM = 1 << 29,
};
/* Auto-Slow monitoring */
enum imx233_as_monitor_t
{
AS_NONE = 0, /* Do not monitor any activity */
AS_CPU_INSTR = 1 << 21, /* Monitor CPU instruction access to AHB */
AS_CPU_DATA = 1 << 22, /* Monitor CPU data access to AHB */
AS_TRAFFIC = 1 << 23, /* Monitor AHB master activity */
AS_TRAFFIC_JAM = 1 << 24, /* Monitor AHB masters (>=3) activity */
AS_APBXDMA = 1 << 25, /* Monitor APBX DMA activity */
AS_APBHDMA = 1 << 26, /* Monitor APBH DMA activity */
AS_PXP = 1 << 27, /* Monitor PXP activity */
AS_DCP = 1 << 28, /* Monitor DCP activity */
AS_ALL = 0xff << 21, /* Monitor all activity */
};
enum imx233_as_div_t
{
AS_DIV_1 = 0,
AS_DIV_2 = 1,
AS_DIV_4 = 2,
AS_DIV_8 = 3,
AS_DIV_16 = 4,
AS_DIV_32 = 5
};
/* can use a mask of clocks */
void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable);
void imx233_clkctrl_is_xtal_enabled(enum imx233_xtal_clk_t xtal_clk, bool enable);
void imx233_clkctrl_init(void);
/* only use it for non-fractional clocks (ie not for IO) */
void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable);
bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t cl);
void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div);
int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk);
void imx233_clkctrl_enable(enum imx233_clock_t clk, bool enable);
bool imx233_clkctrl_is_enabled(enum imx233_clock_t cl);
void imx233_clkctrl_set_div(enum imx233_clock_t clk, int div);
int imx233_clkctrl_get_div(enum imx233_clock_t clk);
/* call with fracdiv=0 to disable it */
void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv);
void imx233_clkctrl_set_frac_div(enum imx233_clock_t clk, int fracdiv);
/* 0 means fractional dividor disable */
int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk);
void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass);
bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk);
void imx233_clkctrl_enable_usb_pll(bool enable);
bool imx233_clkctrl_is_usb_pll_enabled(void);
unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk);
bool imx233_clkctrl_is_emi_sync_enabled(void);
void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div);
enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void);
int imx233_clkctrl_get_frac_div(enum imx233_clock_t clk);
void imx233_clkctrl_set_bypass(enum imx233_clock_t clk, bool bypass);
bool imx233_clkctrl_get_bypass(enum imx233_clock_t clk);
void imx233_clkctrl_enable_usb(bool enable);
bool imx233_clkctrl_is_usb_enabled(void);
/* returns frequency in KHz */
unsigned imx233_clkctrl_get_freq(enum imx233_clock_t clk);
/* auto-slow stuff */
void imx233_clkctrl_set_auto_slow_div(unsigned div);
unsigned imx233_clkctrl_get_auto_slow_div(void);
void imx233_clkctrl_enable_auto_slow(bool enable);
bool imx233_clkctrl_is_auto_slow_enabled(void);
/* can use a mask of clocks */
void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable);
bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor);
#endif /* CLKCTRL_IMX233_H */

8
firmware/target/arm/imx233/creative-zenxfi2/lcd-zenxfi2.c
View file

@ -110,10 +110,10 @@ static inline uint32_t decode_18_to_16(uint32_t a)
static void setup_lcdif_clock(void)
{
/* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */
imx233_clkctrl_enable_clock(CLK_PIX, false);
imx233_clkctrl_set_clock_divisor(CLK_PIX, 1);
imx233_clkctrl_set_bypass_pll(CLK_PIX, true); /* use XTAL */
imx233_clkctrl_enable_clock(CLK_PIX, true);
imx233_clkctrl_enable(CLK_PIX, false);
imx233_clkctrl_set_div(CLK_PIX, 1);
imx233_clkctrl_set_bypass(CLK_PIX, true); /* use XTAL */
imx233_clkctrl_enable(CLK_PIX, true);
}
static void lcd_write_reg(uint32_t reg, uint32_t data)

8
firmware/target/arm/imx233/creative-zenxfi3/lcd-zenxfi3.c
View file

@ -97,10 +97,10 @@ static void setup_lcdif(void)
static void setup_lcdif_clock(void)
{
/* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */
imx233_clkctrl_enable_clock(CLK_PIX, false);
imx233_clkctrl_set_clock_divisor(CLK_PIX, 1);
imx233_clkctrl_set_bypass_pll(CLK_PIX, true); /* use XTAL */
imx233_clkctrl_enable_clock(CLK_PIX, true);
imx233_clkctrl_enable(CLK_PIX, false);
imx233_clkctrl_set_div(CLK_PIX, 1);
imx233_clkctrl_set_bypass(CLK_PIX, true); /* use XTAL */
imx233_clkctrl_enable(CLK_PIX, true);
}
static void lcd_write_reg(uint32_t reg, uint32_t data)

60
firmware/target/arm/imx233/debug-imx233.c
View file

@ -242,22 +242,6 @@ static struct
{ CLK_XBUS, "xbus", false, false, true, false, true }
};
static struct
{
enum imx233_as_monitor_t monitor;
const char *name;
} dbg_as_monitor[] =
{
{ AS_CPU_INSTR, "cpu inst" },
{ AS_CPU_DATA, "cpu data" },
{ AS_TRAFFIC, "traffic" },
{ AS_TRAFFIC_JAM, "traffic jam" },
{ AS_APBXDMA, "apbx" },
{ AS_APBHDMA, "apbh" },
{ AS_PXP, "pxp" },
{ AS_DCP, "dcp" }
};
bool dbg_hw_info_clkctrl(void)
{
lcd_setfont(FONT_SYSFIXED);
@ -287,44 +271,22 @@ bool dbg_hw_info_clkctrl(void)
#define c dbg_clk[i]
lcd_putsf(0, i + 1, "%4s", c.name);
if(c.has_enable)
lcd_putsf(5, i + 1, "%2d", imx233_clkctrl_is_clock_enabled(c.clk));
lcd_putsf(5, i + 1, "%2d", imx233_clkctrl_is_enabled(c.clk));
if(c.has_bypass)
lcd_putsf(8, i + 1, "%2d", imx233_clkctrl_get_bypass_pll(c.clk));
if(c.has_idiv && imx233_clkctrl_get_clock_divisor(c.clk) != 0)
lcd_putsf(10, i + 1, "%4d", imx233_clkctrl_get_clock_divisor(c.clk));
if(c.has_fdiv && imx233_clkctrl_get_fractional_divisor(c.clk) != 0)
lcd_putsf(16, i + 1, "%4d", imx233_clkctrl_get_fractional_divisor(c.clk));
lcd_putsf(8, i + 1, "%2d", imx233_clkctrl_get_bypass(c.clk));
if(c.has_idiv && imx233_clkctrl_get_div(c.clk) != 0)
lcd_putsf(10, i + 1, "%4d", imx233_clkctrl_get_div(c.clk));
if(c.has_fdiv && imx233_clkctrl_get_frac_div(c.clk) != 0)
lcd_putsf(16, i + 1, "%4d", imx233_clkctrl_get_frac_div(c.clk));
if(c.has_freq)
lcd_putsf(21, i + 1, "%9d", imx233_clkctrl_get_clock_freq(c.clk));
lcd_putsf(21, i + 1, "%9d", imx233_clkctrl_get_freq(c.clk));
#undef c
}
int line = ARRAYLEN(dbg_clk) + 1;
lcd_putsf(0, line, "as: %d/%d emi sync: %d", imx233_clkctrl_is_auto_slow_enabled(),
1 << imx233_clkctrl_get_auto_slow_divisor(), imx233_clkctrl_is_emi_sync_enabled());
line++;
lcd_putsf(0, line, "as monitor: ");
int x_off = 12;
bool first = true;
unsigned line_w = lcd_getwidth() / font_get_width(font_get(lcd_getfont()), ' ');
for(unsigned i = 0; i < ARRAYLEN(dbg_as_monitor); i++)
{
if(!imx233_clkctrl_is_auto_slow_monitor_enabled(dbg_as_monitor[i].monitor))
continue;
if(!first)
{
lcd_putsf(x_off, line, ", ");
x_off += 2;
}
first = false;
if((x_off + strlen(dbg_as_monitor[i].name)) > line_w)
{
x_off = 1;
line++;
}
lcd_putsf(x_off, line, "%s", dbg_as_monitor[i].name);
x_off += strlen(dbg_as_monitor[i].name);
}
line++;
if(!imx233_clkctrl_is_auto_slow_enabled())
lcd_putsf(0, line++, "auto-slow: disabled");
else
lcd_putsf(0, line++, "auto-slow: 1/%d", 1 << imx233_clkctrl_get_auto_slow_div());
lcd_update();
yield();

5
firmware/target/arm/imx233/pwm-imx233.c
View file

@ -25,7 +25,7 @@
void imx233_pwm_init(void)
{
imx233_reset_block(&HW_PWM_CTRL);
imx233_clkctrl_enable_xtal(XTAM_PWM, true);
imx233_clkctrl_enable(CLK_PWM, true);
}
bool imx233_pwm_is_channel_enable(int channel)
@ -50,7 +50,8 @@ void imx233_pwm_setup_channel(int channel, int period, int cdiv, int active,
imx233_pwm_enable_channel(channel, false);
/* setup pin */
imx233_pinctrl_setup_vpin(VPIN_PWM(channel), "pwm", PINCTRL_DRIVE_4mA, false);
/* watch the order ! active THEN period */
/* watch the order ! active THEN period
* NOTE: the register value is period-1 */
HW_PWM_ACTIVEn(channel) = BF_OR2(PWM_ACTIVEn, ACTIVE(active), INACTIVE(inactive));
HW_PWM_PERIODn(channel) = BF_OR4(PWM_PERIODn, PERIOD(period - 1),
ACTIVE_STATE(active_state), INACTIVE_STATE(inactive_state), CDIV(cdiv));

8
firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c
View file

@ -168,10 +168,10 @@ static inline uint32_t decode_18_to_16(uint32_t a)
static void setup_lcdif_clock(void)
{
/* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */
imx233_clkctrl_enable_clock(CLK_PIX, false);
imx233_clkctrl_set_clock_divisor(CLK_PIX, 1);
imx233_clkctrl_set_bypass_pll(CLK_PIX, true); /* use XTAL */
imx233_clkctrl_enable_clock(CLK_PIX, true);
imx233_clkctrl_enable(CLK_PIX, false);
imx233_clkctrl_set_div(CLK_PIX, 1);
imx233_clkctrl_set_bypass(CLK_PIX, true); /* use XTAL */
imx233_clkctrl_enable(CLK_PIX, true);
}
static uint32_t i80_read_register(uint32_t data_out)

19
firmware/target/arm/imx233/ssp-imx233.c
View file

@ -114,7 +114,7 @@ void imx233_ssp_start(int ssp)
return;
ssp_in_use[ssp - 1] = true;
/* Gate block */
imx233_reset_block(&SSP_REGn(SSP_CTRL0, ssp));
imx233_ssp_softreset(ssp);
/* Gate dma channel */
imx233_dma_clkgate_channel(APB_SSP(ssp), true);
/* If first block to start, start SSP clock */
@ -123,11 +123,11 @@ void imx233_ssp_start(int ssp)
/** 2.3.1: the clk_ssp maximum frequency is 102.858 MHz */
/* fracdiv = 18 => clk_io = pll = 480Mhz
* intdiv = 5 => clk_ssp = 96Mhz */
imx233_clkctrl_set_fractional_divisor(CLK_IO, 18);
imx233_clkctrl_enable_clock(CLK_SSP, false);
imx233_clkctrl_set_clock_divisor(CLK_SSP, 5);
imx233_clkctrl_set_bypass_pll(CLK_SSP, false); /* use IO */
imx233_clkctrl_enable_clock(CLK_SSP, true);
imx233_clkctrl_set_frac_div(CLK_IO, 18);
imx233_clkctrl_enable(CLK_SSP, false);
imx233_clkctrl_set_div(CLK_SSP, 5);
imx233_clkctrl_set_bypass(CLK_SSP, false); /* use IO */
imx233_clkctrl_enable(CLK_SSP, true);
}
ssp_nr_in_use++;
}
@ -145,16 +145,13 @@ void imx233_ssp_stop(int ssp)
/* If last block to stop, stop SSP clock */
ssp_nr_in_use--;
if(ssp_nr_in_use == 0)
{
imx233_clkctrl_enable_clock(CLK_SSP, false);
imx233_clkctrl_set_fractional_divisor(CLK_IO, 0);
}
imx233_clkctrl_enable(CLK_SSP, false);
}
void imx233_ssp_softreset(int ssp)
{
ASSERT_SSP(ssp)
imx233_reset_block(&HW_SSP_CTRL0(ssp));
imx233_reset_block(&SSP_REGn(SSP_CTRL0, ssp));
}
void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout)

48
firmware/target/arm/imx233/system-imx233.c
View file

@ -105,8 +105,12 @@ void system_init(void)
/* NOTE: don't use anything here that might require tick task !
* It is initialized by kernel_init *after* system_init().
* The main() will naturally set cpu speed to normal after kernel_init()
* so don't bother if the cpu is running at 24MHz here. */
imx233_clkctrl_enable_clock(CLK_PLL, true);
* so don't bother if the cpu is running at 24MHz here.
* Make sure IO clock is running at expected speed */
imx233_clkctrl_init();
imx233_clkctrl_enable(CLK_PLL, true);
imx233_clkctrl_set_frac_div(CLK_IO, 18); // clk_io@clk_pll
imx233_rtc_init();
imx233_icoll_init();
imx233_pinctrl_init();
@ -119,19 +123,14 @@ void system_init(void)
imx233_power_init();
imx233_i2c_init();
imx233_clkctrl_enable_auto_slow_monitor(AS_CPU_INSTR, true);
imx233_clkctrl_enable_auto_slow_monitor(AS_CPU_DATA, true);
imx233_clkctrl_enable_auto_slow_monitor(AS_TRAFFIC, true);
imx233_clkctrl_enable_auto_slow_monitor(AS_TRAFFIC_JAM, true);
imx233_clkctrl_enable_auto_slow_monitor(AS_APBXDMA, true);
imx233_clkctrl_enable_auto_slow_monitor(AS_APBHDMA, true);
imx233_clkctrl_set_auto_slow_divisor(AS_DIV_8);
imx233_clkctrl_enable_auto_slow(true);
/* make sure auto-slow is disable now, we don't know at which frequency we
* are running and auto-slow could violate constraints on {xbus,hbus} */
imx233_clkctrl_enable_auto_slow(false);
imx233_clkctrl_set_auto_slow_div(BV_CLKCTRL_HBUS_SLOW_DIV__BY8);
cpu_frequency = imx233_clkctrl_get_clock_freq(CLK_CPU);
cpu_frequency = imx233_clkctrl_get_freq(CLK_CPU);
#if !defined(BOOTLOADER) &&(defined(SANSA_FUZEPLUS) || \
defined(CREATIVE_ZENXFI3) || defined(CREATIVE_ZENXFI2))
#if CONFIG_TUNER
fmradio_i2c_init();
#endif
}
@ -210,7 +209,6 @@ void set_cpu_frequency(long frequency)
if(prof->cpu_freq == 0)
return;
/* disable auto-slow (enable back afterwards) */
bool as = imx233_clkctrl_is_auto_slow_enabled();
imx233_clkctrl_enable_auto_slow(false);
/* WARNING watch out the order ! */
@ -221,28 +219,28 @@ void set_cpu_frequency(long frequency)
/* Change ARM cache timings */
imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings);
/* Switch CPU to crystal at 24MHz */
imx233_clkctrl_set_bypass_pll(CLK_CPU, true);
imx233_clkctrl_set_bypass(CLK_CPU, true);
/* Program CPU divider for PLL */
imx233_clkctrl_set_fractional_divisor(CLK_CPU, prof->cpu_fdiv);
imx233_clkctrl_set_clock_divisor(CLK_CPU, prof->cpu_idiv);
imx233_clkctrl_set_frac_div(CLK_CPU, prof->cpu_fdiv);
imx233_clkctrl_set_div(CLK_CPU, prof->cpu_idiv);
/* Change the HBUS divider to its final value */
imx233_clkctrl_set_clock_divisor(CLK_HBUS, prof->hbus_div);
imx233_clkctrl_set_div(CLK_HBUS, prof->hbus_div);
/* Switch back CPU to PLL */
imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
imx233_clkctrl_set_bypass(CLK_CPU, false);
/* Set the new EMI frequency */
imx233_emi_set_frequency(prof->emi_freq);
}
else
{
/* Switch CPU to crystal at 24MHz */
imx233_clkctrl_set_bypass_pll(CLK_CPU, true);
imx233_clkctrl_set_bypass(CLK_CPU, true);
/* Program HBUS divider to its final value */
imx233_clkctrl_set_clock_divisor(CLK_HBUS, prof->hbus_div);
imx233_clkctrl_set_div(CLK_HBUS, prof->hbus_div);
/* Program CPU divider for PLL */
imx233_clkctrl_set_fractional_divisor(CLK_CPU, prof->cpu_fdiv);
imx233_clkctrl_set_clock_divisor(CLK_CPU, prof->cpu_idiv);
imx233_clkctrl_set_frac_div(CLK_CPU, prof->cpu_fdiv);
imx233_clkctrl_set_div(CLK_CPU, prof->cpu_idiv);
/* Switch back CPU to PLL */
imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
imx233_clkctrl_set_bypass(CLK_CPU, false);
/* Set the new EMI frequency */
imx233_emi_set_frequency(prof->emi_freq);
/* Change ARM cache timings */
@ -251,7 +249,7 @@ void set_cpu_frequency(long frequency)
imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo);
}
/* enable auto slow again */
imx233_clkctrl_enable_auto_slow(as);
imx233_clkctrl_enable_auto_slow(true);
/* update frequency */
cpu_frequency = frequency;
}

2
firmware/target/arm/imx233/timrot-imx233.c
View file

@ -62,5 +62,5 @@ void imx233_timrot_init(void)
{
imx233_reset_block(&HW_TIMROT_ROTCTRL);
/* enable xtal path to timrot */
imx233_clkctrl_enable_xtal(XTAL_TIMROT, true);
imx233_clkctrl_enable(CLK_TIMROT, true);
}

4
firmware/target/arm/imx233/usb-imx233.c
View file

@ -68,7 +68,7 @@ void usb_enable(bool on)
{
if(on)
{
imx233_clkctrl_enable_usb_pll(true);
imx233_clkctrl_enable_usb(true);
imx233_enable_usb_phy(true);
imx233_enable_usb_controller(true);
usb_core_init();
@ -78,6 +78,6 @@ void usb_enable(bool on)
usb_core_exit();
imx233_enable_usb_controller(false);
imx233_enable_usb_phy(false);
imx233_clkctrl_enable_usb_pll(false);
imx233_clkctrl_enable_usb(false);
}
}