mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-10-13 10:07:38 -04:00
FS#10048 : enable MMU and data cache on Sansa AMS to give a major speed up
- cache IRAM and DRAM - map IRAM just next to DRAM to remove the need for -mlong-calls and reduce binsize - tweak delays in Fuze button code - tweak delays in Clip button code (down button sometimes doesn't respond anyway : an alternate driver is being worked on) Before reporting any problem, please check your filesystem or format your player from the OF git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21228 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
parent
20a78a36f3
commit
f504153857
13 changed files with 84 additions and 54 deletions
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@ -36,6 +36,8 @@
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#include "power.h"
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int show_logo(void);
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void main(void) __attribute__((naked, noreturn));
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void main(void)
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{
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unsigned char* loadbuffer;
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@ -374,6 +374,7 @@ target/arm/as3525/usb-as3525.c
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target/arm/as3525/dma-pl081.c
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target/arm/as3525/ascodec-as3525.c
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#ifndef BOOTLOADER
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target/arm/mmu-arm.S
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drivers/generic_i2c.c
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target/arm/adc-as3514.c
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target/arm/as3525/audio-as3525.c
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@ -27,9 +27,11 @@
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/* we put the codec buffer in IRAM */
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#define AMS_LOWMEM
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#endif
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/* these addresses are valid after mapping through the MMU */
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/* Virtual addresses */
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/* Do not apply to the bootloader, which uses physical addresses (no MMU) */
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#define DRAM_ORIG 0x30000000
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#define IRAM_ORIG 0x0
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#define IRAM_ORIG (DRAM_ORIG + DRAM_SIZE) /* IRAM is mapped just next to DRAM */
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#define DRAM_SIZE (MEMORYSIZE * 0x100000)
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#define IRAM_SIZE 0x50000
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@ -40,8 +42,7 @@
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#define ECCBYTES 3
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/* AS352X MMU Page Table Entries */
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/* to be implemented */
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#define TTB_SIZE 0x0
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#define TTB_SIZE 0x4000
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#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
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@ -493,4 +494,7 @@ interface */
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#define I2SOUT_CLEAR (*(volatile unsigned char*)(I2SOUT_BASE+0x10))
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#define I2SOUT_DATA (volatile unsigned long*)(I2SOUT_BASE+0x14)
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/* PCM addresses for obtaining buffers will be what DMA is using (physical) */
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#define HAVE_PCM_DMA_ADDRESS
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#endif /*__AS3525_H__*/
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@ -55,6 +55,12 @@ SECTIONS
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{
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loadaddress = DRAM_ORIG;
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.vectors :
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{
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_vectors_start = .;
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*(.init.text)
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} > DRAM
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.text :
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{
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_loadaddress = .;
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@ -83,14 +89,6 @@ SECTIONS
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*(.eh_frame)
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}
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.vectors IRAMORIG:
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{
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_vectors_start = .;
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*(.init.text)
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} > IRAM AT > DRAM
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_vectorscopy = LOADADDR(.vectors);
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.iram :
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{
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_iramstart = .;
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@ -595,7 +595,7 @@ static int sd_select_bank(signed char bank)
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dma_enable_channel(0, card_data, MCI_FIFO(INTERNAL_AS3525), DMA_PERI_SD,
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DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
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MCI_DATA_TIMER(INTERNAL_AS3525) = 0x1000000; /* FIXME: arbitrary */
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MCI_DATA_TIMER(INTERNAL_AS3525) = 0xffffffff;/* FIXME: arbitrary */
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MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
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MCI_DATA_CTRL(INTERNAL_AS3525) = (1<<0) /* enable */ |
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(0<<1) /* transfer direction */ |
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@ -618,7 +618,8 @@ static int sd_select_bank(signed char bank)
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}
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#define UNALIGNED_NUM_SECTORS 10
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static int32_t aligned_buffer[UNALIGNED_NUM_SECTORS* (SECTOR_SIZE / 4)];
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static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SECTOR_SIZE] __attribute__((aligned(32))); /* align on cache line size */
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static unsigned char *uncached_buffer = UNCACHED_ADDR(aligned_buffer);
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static int sd_transfer_sectors(IF_MV2(int drive,) unsigned long start,
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int count, void* buf, const bool write)
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@ -627,7 +628,6 @@ static int sd_transfer_sectors(IF_MV2(int drive,) unsigned long start,
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const int drive = 0;
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#endif
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int ret = 0;
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bool unaligned_transfer = (int)buf & 3;
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/* skip SanDisk OF */
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if (drive == INTERNAL_AS3525)
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@ -693,16 +693,11 @@ static int sd_transfer_sectors(IF_MV2(int drive,) unsigned long start,
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transfer = BLOCKS_PER_BANK - bank_start;
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}
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if(unaligned_transfer)
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{
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dma_buf = aligned_buffer;
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if(transfer > UNALIGNED_NUM_SECTORS)
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transfer = UNALIGNED_NUM_SECTORS;
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if(write)
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memcpy(aligned_buffer, buf, transfer * SECTOR_SIZE);
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}
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else /* Aligned transfers are faster : no memcpy */
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dma_buf = buf;
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dma_buf = aligned_buffer;
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if(transfer > UNALIGNED_NUM_SECTORS)
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transfer = UNALIGNED_NUM_SECTORS;
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if(write)
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memcpy(uncached_buffer, buf, transfer * SECTOR_SIZE);
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/* Set bank_start to the correct unit (blocks or bytes) */
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if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
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@ -734,8 +729,8 @@ static int sd_transfer_sectors(IF_MV2(int drive,) unsigned long start,
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wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
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if(!retry)
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{
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if(unaligned_transfer && !write)
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memcpy(buf, aligned_buffer, transfer * SECTOR_SIZE);
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if(!write)
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memcpy(buf, uncached_buffer, transfer * SECTOR_SIZE);
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buf += transfer * SECTOR_SIZE;
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start += transfer;
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count -= transfer;
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@ -6,17 +6,11 @@ OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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STARTUP(target/arm/crt0.o)
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/*
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No need for DRAM in our bootloader
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - TTB_SIZE
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#define DRAMORIG 0x30000000
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*/
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#define IRAMORIG 0x81000000
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#define IRAMSIZE 0x50000
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MEMORY
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{
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/*DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE*/
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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}
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@ -28,6 +28,7 @@
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#include "panic.h"
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#include "as3514.h"
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#include "audiohw.h"
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#include "mmu-arm.h"
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#define MAX_TRANSFER (4*((1<<11)-1)) /* maximum data we can transfer via DMA
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* i.e. 32 bits at once (size of I2SO_DATA)
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@ -69,6 +70,7 @@ static void play_start_pcm(void)
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CGU_PERI |= CGU_I2SOUT_APB_CLOCK_ENABLE;
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CGU_AUDIO |= (1<<11);
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clean_dcache_range((void*)addr, size); /* force write back */
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dma_enable_channel(1, (void*)addr, (void*)I2SOUT_DATA, DMA_PERI_I2SOUT,
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DMAC_FLOWCTRL_DMAC_MEM_TO_PERI, true, false, size >> 2, DMA_S1,
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dma_callback);
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return (const void*)dma_start_addr;
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}
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#ifdef HAVE_PCM_DMA_ADDRESS
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void * pcm_dma_addr(void *addr)
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{
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if (addr != NULL)
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addr = UNCACHED_ADDR(addr);
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return addr;
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}
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#endif
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/****************************************************************************
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** Recording DMA transfer
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@ -46,8 +46,9 @@ int button_read_device(void)
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/* This is a keypad using C4-C6 as columns and B0-B2 as rows */
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GPIOC_PIN(4) = (1<<4);
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asm volatile("nop\nnop\nnop\nnop\nnop\n"); /* small delay */
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/* C4B0 is unused */
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(void)GPIOB_PIN(0); /* C4B0 is unused */
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if (GPIOB_PIN(1))
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result |= BUTTON_VOL_UP;
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GPIOC_PIN(4) = 0x00;
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GPIOC_PIN(5) = (1<<5);
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asm volatile("nop\nnop\nnop\nnop\nnop\n"); /* small delay */
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if (GPIOB_PIN(0))
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result |= BUTTON_LEFT;
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GPIOC_PIN(5) = 0x00;
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GPIOC_PIN(6) = (1<<6);
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asm volatile("nop\nnop\nnop\nnop\nnop\n"); /* small delay */
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if (GPIOB_PIN(0))
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result |= BUTTON_DOWN;
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@ -150,7 +150,7 @@ bool button_hold(void)
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static void button_delay(void)
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{
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int i = 24;
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int i = 50;
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while(i--) asm volatile ("nop\n");
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}
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@ -28,6 +28,9 @@
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#include "clock-target.h"
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#include "fmradio_i2c.h"
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#include "button-target.h"
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#ifndef BOOTLOADER
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#include "mmu-arm.h"
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#endif
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */
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}
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#else
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void memory_init(void)
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{
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ttb_init();
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/* map every region to itself, uncached */
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map_section(0, 0, 4096, CACHE_NONE);
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/* IRAM */
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map_section(0, IRAM_ORIG, 1, CACHE_ALL);
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map_section(0, UNCACHED_ADDR(IRAM_ORIG), 1, CACHE_NONE);
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/* DRAM */
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map_section(0x30000000, DRAM_ORIG, MEMORYSIZE, CACHE_ALL);
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map_section(0x30000000, UNCACHED_ADDR(DRAM_ORIG), MEMORYSIZE, CACHE_NONE);
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/* map 1st mbyte of DRAM at 0x0 to have exception vectors available */
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map_section(0x30000000, 0, 1, CACHE_ALL);
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enable_mmu();
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}
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#endif
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void system_init(void)
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CCU_SRL = CCU_SRL_MAGIC_NUMBER;
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CCU_SRC = CCU_SRL = 0;
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CCU_SCON = 1; /* AHB master's priority configuration :
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TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
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CGU_PROC = 0; /* fclk 24 MHz */
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CGU_PERI &= ~0x7f; /* pclk 24 MHz */
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asm volatile(
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"mov r0, #0 \n"
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"mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */
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"mrc p15, 0, r0, c1, c0 \n" /* control register */
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"bic r0, r0, #3<<30 \n" /* clears bus bits & sets fastbus */
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"orr r0, r0, #1<<12 \n" /* enable icache */
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"bic r0, r0, #3<<30 \n" /* clears bus bits : sets fastbus */
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"mcr p15, 0, r0, c1, c0 \n"
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: : : "r0" );
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@ -25,4 +25,10 @@
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#include "clock-target.h" /* CPUFREQ_* are defined here */
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#ifdef BOOTLOADER
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#define UNCACHED_ADDR(a) (a)
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#else
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#define UNCACHED_ADDR(a) (a + 0x10000000)
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#endif
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#endif /* SYSTEM_TARGET_H */
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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#if CONFIG_CPU==AS3525 && !defined(BOOTLOADER)
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/* relocate vectors */
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mov r1, #0 @ destination
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ldr r2, =_vectorscopy @ source
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ldr r3, =_vectorsend @ end
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1: ldr r0, [r2], #4
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str r0, [r1], #4
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cmp r1, r3
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bne 1b
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/* Setup MMU : has to be done before accessing IRAM ! */
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bl memory_init
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/* Zero out IBSS */
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ldr r2, =_iedata
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12
tools/configure
vendored
12
tools/configure
vendored
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@ -259,7 +259,7 @@ arm7tdmicc () {
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arm9tdmicc () {
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prefixtools arm-elf-
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GCCOPTS="$CCOPTS -mcpu=arm9tdmi"
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if test "$modelname" != "gigabeatf"; then
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if test "$modelname" != "gigabeatf" -a "$t_manufacturer" != "as3525"; then
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GCCOPTS="$GCCOPTS -mlong-calls"
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fi
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GCCOPTIMIZE="-fomit-frame-pointer"
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modelname="clip"
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target="-DSANSA_CLIP"
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memory=2
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arm9tdmicc
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bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
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bmp2rb_native="$bmp2rb_mono"
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tool="$rootdir/tools/scramble -add=clip"
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t_cpu="arm"
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t_manufacturer="as3525"
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t_model="sansa-clip"
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arm9tdmicc
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;;
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modelname="e200v2"
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target="-DSANSA_E200V2"
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memory=8
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arm9tdmicc
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bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
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bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
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tool="$rootdir/tools/scramble -add=e2v2"
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t_cpu="arm"
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t_manufacturer="as3525"
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t_model="sansa-e200v2"
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arm9tdmicc
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;;
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modelname="m200v4"
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target="-DSANSA_M200V4"
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memory=2
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arm9tdmicc
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bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
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bmp2rb_native="$bmp2rb_mono"
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tool="$rootdir/tools/scramble -add=m2v4"
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t_cpu="arm"
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t_manufacturer="as3525"
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t_model="sansa-m200v4"
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arm9tdmicc
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;;
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@ -1797,7 +1797,6 @@ fi
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modelname="fuze"
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target="-DSANSA_FUZE"
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memory=8
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arm9tdmicc
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bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
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bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
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tool="$rootdir/tools/scramble -add=fuze"
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t_cpu="arm"
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t_manufacturer="as3525"
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t_model="sansa-fuze"
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arm9tdmicc
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;;
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@ -1818,7 +1818,6 @@ fi
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modelname="c200v2"
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target="-DSANSA_C200V2"
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memory=2 # as per OF diagnosis mode
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arm9tdmicc
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bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
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bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
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tool="$rootdir/tools/scramble -add=c2v2"
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@ -1834,6 +1833,7 @@ fi
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t_cpu="arm"
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t_manufacturer="as3525"
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t_model="sansa-c200v2"
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arm9tdmicc
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;;
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60|Clipv2|clipv2)
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