From f428c491d19c983e897adce5c900480543014421 Mon Sep 17 00:00:00 2001 From: Marcin Bukat Date: Fri, 25 Sep 2026 11:21:09 +0200 Subject: [PATCH] rk27xx: keep the NAND controller clocked system_init() gates the clocks of modules a firmware build does not use, and the list included the NAND controller's HCLK. Once the NAND is storage, the first access to the controller - flash_init() writing FMWAIT at 0x180e8004 - takes a data abort on the unclocked peripheral. No rk27xx target stored to NAND before, which is why this never showed. The LCDC clock in the same list stays gated: the firmware draws with it gated, the MCU interface running from the LCDC HCLK, which is not. Co-Authored-By: Claude Opus 5.5 Change-Id: I52a4dc9e63fe5b89c85b60dc3ef77d74528dc06f --- firmware/target/arm/rk27xx/system-rk27xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c index ff0aaf38a9..6cbc3aa9ae 100644 --- a/firmware/target/arm/rk27xx/system-rk27xx.c +++ b/firmware/target/arm/rk27xx/system-rk27xx.c @@ -129,7 +129,8 @@ void system_init(void) MCSDR_T_RP = 1; /* precharge period */ MCSDR_T_RCD = 1; /* active to RD/WR delay */ - /* turn off clock for unused modules */ + /* turn off clock for unused modules - not the NAND controller's: the + * FTL uses it, and a register access with its HCLK gated aborts */ SCU_CLKCFG |= CLKCFG_WDT | /* WDT pclk */ CLKCFG_RTC | /* RTC pclk */ CLKCFG_HSADC | /* HS_ADC clock */ @@ -140,7 +141,6 @@ void system_init(void) CLKCFG_VIP | /* VIP clock */ CLKCFG_HCLK_VIP | /* VIP HCLK */ CLKCFG_LCDC | /* LCDC clock */ - CLKCFG_NAND | /* NAND HCLK */ CLKCFG_UHC | /* USB host HCLK */ CLKCFG_DSP | /* DSP clock */ CLKCFG_OTP; /* OTP clock (dunno what it is */