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M:Robe 500/M66591: Add support for full-speed USB transfers, and fix the UART interrupt clearing.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22095 a1c6a512-1295-4272-9138-f99709370657
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5c882be608
commit
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2 changed files with 43 additions and 20 deletions
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@ -41,6 +41,11 @@
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/*******************************************************************************
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* These are the driver specific defines.
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******************************************************************************/
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/* This define is primarily intended for testing, using HISPEED all the time
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* should be acceptable since the defice should down-train if the host does not
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* support HISPEED.
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*/
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#define HISPEED
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/* Right now sending blocks till the full transfer has completed, this needs to
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@ -134,10 +139,12 @@ static int pipe_buffer_size (int pipe) {
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}
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#endif
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/* This function returns the maximum packet size for each endpoint/pipe. It is
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* Currently only setup to support Highspeed mode.
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/* This function returns the maximum packet size for each endpoint/pipe. The
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* max packet size is dependent on whether the device is running High or Full
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* speed.
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*/
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static int pipe_maxpack_size (int pipe) {
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if( (M66591_HSFS & 0xFF) == 0x03 ) { /* Device is running Highspeed */
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switch(pipe) {
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case 0:
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/* DCP max packet size is configurable */
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@ -153,6 +160,23 @@ static int pipe_maxpack_size (int pipe) {
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default:
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return 0;
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}
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} else { /* Device is running Full speed */
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switch(pipe) {
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case 0:
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/* DCP max packet size is configurable */
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return M66591_DCP_MXPKSZ;
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case 1:
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case 2:
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case 3:
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case 4:
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return 64;
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case 5:
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case 6:
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return 64;
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default:
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return 0;
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}
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}
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}
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/* This is a helper function that is only called from the interupt handler. It
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@ -461,7 +485,7 @@ void USB_DEVICE(void) {
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case CTRL_RTDS:
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case CTRL_WTDS:
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case CTRL_WTND:
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// If data is not valid stop
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/* If data is not valid stop */
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if(!(M66591_INTSTAT_MAIN & (1<<3)) ) {
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logf("mxx: CTRT interrupt but VALID is false");
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break;
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@ -471,7 +495,7 @@ void USB_DEVICE(void) {
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case CTRL_RTSS:
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case CTRL_WTSS:
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pipe_handshake(0, PIPE_SHAKE_BUF);
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M66591_DCPCTRL |= 1<<2; // Set CCPL
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M66591_DCPCTRL |= 1<<2; /* Set CCPL */
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break;
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default:
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logf("mxx: CTRT with unknown CTSQ");
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@ -156,6 +156,7 @@ int uart1_gets_queue(char *str, int size)
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/* UART1 receive/transmit interupt handler */
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void UART1(void)
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{
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IO_INTC_IRQ0 = INTR_IRQ0_UART1; /* Clear the interrupt first */
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while (IO_UART1_RFCR & 0x3f)
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{
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if (uart1_receive_count > RECEIVE_RING_SIZE)
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@ -176,6 +177,4 @@ void UART1(void)
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IO_UART1_DTRR=uart1_send_buffer_ring[uart1_send_read++];
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uart1_send_count--;
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}
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IO_INTC_IRQ0 = INTR_IRQ0_UART1;
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}
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