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Submit first part of FS#12154. Whitespace removal and correction of several defines in WM8758 driver according to data sheet, no functional change. Thanks to Seheon Ryu.

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30024 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Andree Buschmann 2011-06-20 18:37:51 +00:00
parent f2ef42c1da
commit f0c032a523
3 changed files with 119 additions and 102 deletions
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1
docs/CREDITS
View file

@ -596,6 +596,7 @@ Ophir Lojkine
Stephan Grossklass Stephan Grossklass
John Morris John Morris
Sean Bartell Sean Bartell
Seheon Ryu
The libmad team The libmad team
The wavpack team The wavpack team

41
firmware/drivers/audio/wm8758.c
View file

@ -130,18 +130,18 @@ void audiohw_preinit(void)
wmcodec_write(RESET, RESET_RESET); wmcodec_write(RESET, RESET_RESET);
wmcodec_write(PWRMGMT1, PWRMGMT1_PLLEN | PWRMGMT1_BIASEN wmcodec_write(PWRMGMT1, PWRMGMT1_PLLEN | PWRMGMT1_BIASEN
| PWRMGMT1_VMIDSEL_5K); | PWRMGMT1_VMIDSEL_10K);
wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN); wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN);
wmcodec_write(PWRMGMT3, PWRMGMT3_LOUT2EN | PWRMGMT3_ROUT2EN wmcodec_write(PWRMGMT3, PWRMGMT3_LOUT2EN | PWRMGMT3_ROUT2EN
| PWRMGMT3_RMIXEN | PWRMGMT3_LMIXEN | PWRMGMT3_RMIXEN | PWRMGMT3_LMIXEN
| PWRMGMT3_DACENR | PWRMGMT3_DACENL); | PWRMGMT3_DACENR | PWRMGMT3_DACENL);
wmcodec_write(AINTFCE, AINTFCE_IWL_16BIT | AINTFCE_FORMAT_I2S); wmcodec_write(AINTFCE, AINTFCE_IWL_16BIT | AINTFCE_FORMAT_I2S);
wmcodec_write(OUTCTRL, OUTCTRL_VROI); wmcodec_write(OUTCTRL, OUTCTRL_VROI);
wmcodec_write(CLKCTRL, CLKCTRL_MS); /* WM8758 is clock master */ wmcodec_write(CLKCTRL, CLKCTRL_MS); /* WM8758 is clock master */
audiohw_set_frequency(HW_FREQ_44); audiohw_set_frequency(HW_FREQ_44);
wmcodec_write(LOUTMIX, LOUTMIX_DACL2LMIX); wmcodec_write(LOUTMIX, LOUTMIX_DACL2LMIX);
wmcodec_write(ROUTMIX, ROUTMIX_DACR2RMIX); wmcodec_write(ROUTMIX, ROUTMIX_DACR2RMIX);
} }
@ -149,7 +149,7 @@ void audiohw_preinit(void)
void audiohw_postinit(void) void audiohw_postinit(void)
{ {
wmcodec_write(PWRMGMT1, PWRMGMT1_PLLEN | PWRMGMT1_BIASEN wmcodec_write(PWRMGMT1, PWRMGMT1_PLLEN | PWRMGMT1_BIASEN
| PWRMGMT1_VMIDSEL_75K); | PWRMGMT1_VMIDSEL_100K);
/* lower the VMID power consumption */ /* lower the VMID power consumption */
audiohw_mute(false); audiohw_mute(false);
} }
@ -159,12 +159,12 @@ void audiohw_set_master_vol(int vol_l, int vol_r)
int dac_l, amp_l, dac_r, amp_r; int dac_l, amp_l, dac_r, amp_r;
get_volume_params(vol_l, &dac_l, &amp_l); get_volume_params(vol_l, &dac_l, &amp_l);
get_volume_params(vol_r, &dac_r, &amp_r); get_volume_params(vol_r, &dac_r, &amp_r);
/* set DAC /* set DAC
Important: DAC is global and will also affect lineout */ Important: DAC is global and will also affect lineout */
wmcodec_write(LDACVOL, dac_l); wmcodec_write(LDACVOL, dac_l);
wmcodec_write(RDACVOL, dac_r | RDACVOL_DACVU); wmcodec_write(RDACVOL, dac_r | RDACVOL_DACVU);
/* set headphone amp OUT1 */ /* set headphone amp OUT1 */
wmcodec_write(LOUT1VOL, amp_l | LOUT1VOL_LOUT1ZC); wmcodec_write(LOUT1VOL, amp_l | LOUT1VOL_LOUT1ZC);
wmcodec_write(ROUT1VOL, amp_r | ROUT1VOL_ROUT1ZC | ROUT1VOL_OUT1VU); wmcodec_write(ROUT1VOL, amp_r | ROUT1VOL_ROUT1ZC | ROUT1VOL_OUT1VU);
@ -175,7 +175,7 @@ void audiohw_set_lineout_vol(int vol_l, int vol_r)
int dac_l, amp_l, dac_r, amp_r; int dac_l, amp_l, dac_r, amp_r;
get_volume_params(vol_l, &dac_l, &amp_l); get_volume_params(vol_l, &dac_l, &amp_l);
get_volume_params(vol_r, &dac_r, &amp_r); get_volume_params(vol_r, &dac_r, &amp_r);
/* set lineout amp OUT2 */ /* set lineout amp OUT2 */
wmcodec_write(LOUT2VOL, amp_l | LOUT2VOL_LOUT2ZC); wmcodec_write(LOUT2VOL, amp_l | LOUT2VOL_LOUT2ZC);
wmcodec_write(ROUT2VOL, amp_r | ROUT2VOL_ROUT2ZC | ROUT2VOL_OUT2VU); wmcodec_write(ROUT2VOL, amp_r | ROUT2VOL_ROUT2ZC | ROUT2VOL_OUT2VU);
@ -186,7 +186,7 @@ void audiohw_enable_lineout(bool enable)
/* Initialize data without lineout enabling. */ /* Initialize data without lineout enabling. */
int pwrmgmt3_data = PWRMGMT3_RMIXEN | PWRMGMT3_LMIXEN int pwrmgmt3_data = PWRMGMT3_RMIXEN | PWRMGMT3_LMIXEN
| PWRMGMT3_DACENR | PWRMGMT3_DACENL; | PWRMGMT3_DACENR | PWRMGMT3_DACENL;
/* Set lineout (OUT2), if enabled. */ /* Set lineout (OUT2), if enabled. */
if (enable) if (enable)
pwrmgmt3_data |= PWRMGMT3_LOUT2EN | PWRMGMT3_ROUT2EN; pwrmgmt3_data |= PWRMGMT3_LOUT2EN | PWRMGMT3_ROUT2EN;
@ -209,13 +209,13 @@ void audiohw_set_bass_cutoff(int value)
void audiohw_set_treble(int value) void audiohw_set_treble(int value)
{ {
eq5_reg = (eq5_reg & ~EQ_GAIN_MASK) | EQ_GAIN_VALUE(value); eq5_reg = (eq5_reg & ~EQ_GAIN_MASK) | EQ_GAIN_VALUE(value);
wmcodec_write(EQ5, eq5_reg); wmcodec_write(EQ5, eq5_reg);
} }
void audiohw_set_treble_cutoff(int value) void audiohw_set_treble_cutoff(int value)
{ {
eq5_reg = (eq5_reg & ~EQ_CUTOFF_MASK) | EQ_CUTOFF_VALUE(value); eq5_reg = (eq5_reg & ~EQ_CUTOFF_MASK) | EQ_CUTOFF_VALUE(value);
wmcodec_write(EQ5, eq5_reg); wmcodec_write(EQ5, eq5_reg);
} }
/* Nice shutdown of WM8758 codec */ /* Nice shutdown of WM8758 codec */
@ -232,10 +232,10 @@ void audiohw_close(void)
void audiohw_set_frequency(int fsel) void audiohw_set_frequency(int fsel)
{ {
/* CLKCTRL_MCLKDIV_MASK and ADDCTRL_SR_MASK don't overlap, /* CLKCTRL_MCLKDIV_MASK and ADDCTRL_SR_MASK don't overlap,
so they can both fit in one byte. Bit 0 selects PLL so they can both fit in one byte. Bit 0 selects PLL
configuration via pll_setups. configuration via pll_setups.
*/ */
static const unsigned char freq_setups[HW_NUM_FREQ] = static const unsigned char freq_setups[HW_NUM_FREQ] =
{ {
[HW_FREQ_48] = CLKCTRL_MCLKDIV_2 | ADDCTRL_SR_48kHz | 1, [HW_FREQ_48] = CLKCTRL_MCLKDIV_2 | ADDCTRL_SR_48kHz | 1,
[HW_FREQ_44] = CLKCTRL_MCLKDIV_2 | ADDCTRL_SR_48kHz, [HW_FREQ_44] = CLKCTRL_MCLKDIV_2 | ADDCTRL_SR_48kHz,
@ -248,11 +248,11 @@ void audiohw_set_frequency(int fsel)
[HW_FREQ_8] = CLKCTRL_MCLKDIV_12 | ADDCTRL_SR_8kHz | 1 [HW_FREQ_8] = CLKCTRL_MCLKDIV_12 | ADDCTRL_SR_8kHz | 1
}; };
/* Each PLL configuration is an array consisting of /* Each PLL configuration is an array consisting of
{ PLLN, PLLK1, PLLK2, PLLK3 }. The WM8983 datasheet requires { PLLN, PLLK1, PLLK2, PLLK3 }. The WM8983 datasheet requires
5 < PLLN < 13, and states optimum is PLLN = 8, f2 = 90 MHz 5 < PLLN < 13, and states optimum is PLLN = 8, f2 = 90 MHz
*/ */
static const unsigned short pll_setups[2][4] = static const unsigned short pll_setups[2][4] =
{ {
/* f1 = 12 MHz, R = 7.5264, f2 = 90.3168 MHz, fPLLOUT = 22.5792 MHz */ /* f1 = 12 MHz, R = 7.5264, f2 = 90.3168 MHz, fPLLOUT = 22.5792 MHz */
{ PLLN_PLLPRESCALE | 0x7, 0x21, 0x161, 0x26 }, { PLLN_PLLPRESCALE | 0x7, 0x21, 0x161, 0x26 },
@ -267,12 +267,12 @@ void audiohw_set_frequency(int fsel)
wmcodec_write(PLLN + i, pll_setups[freq_setups[fsel] & 1][i]); wmcodec_write(PLLN + i, pll_setups[freq_setups[fsel] & 1][i]);
/* CLKCTRL_MCLKDIV divides fPLLOUT to get SYSCLK (256 * sample rate) */ /* CLKCTRL_MCLKDIV divides fPLLOUT to get SYSCLK (256 * sample rate) */
wmcodec_write(CLKCTRL, CLKCTRL_CLKSEL wmcodec_write(CLKCTRL, CLKCTRL_CLKSEL
| (freq_setups[fsel] & CLKCTRL_MCLKDIV_MASK) | (freq_setups[fsel] & CLKCTRL_MCLKDIV_MASK)
| CLKCTRL_BCLKDIV_2 | CLKCTRL_MS); | CLKCTRL_BCLKDIV_2 | CLKCTRL_MS);
/* set ADC and DAC filter characteristics according to sample rate */ /* set ADC and DAC filter characteristics according to sample rate */
wmcodec_write(ADDCTRL, (freq_setups[fsel] & ADDCTRL_SR_MASK) wmcodec_write(ADDCTRL, (freq_setups[fsel] & ADDCTRL_SR_MASK)
| ADDCTRL_SLOWCLKEN); | ADDCTRL_SLOWCLKEN);
/* SLOWCLK enabled for zero cross timeout to work */ /* SLOWCLK enabled for zero cross timeout to work */
} }
@ -280,7 +280,7 @@ void audiohw_set_frequency(int fsel)
void audiohw_enable_recording(bool source_mic) void audiohw_enable_recording(bool source_mic)
{ {
(void)source_mic; /* We only have a line-in (I think) */ (void)source_mic; /* We only have a line-in (I think) */
wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN
| PWRMGMT2_INPGAENR | PWRMGMT2_INPGAENL | PWRMGMT2_INPGAENR | PWRMGMT2_INPGAENL
| PWRMGMT2_ADCENR | PWRMGMT2_ADCENL); | PWRMGMT2_ADCENR | PWRMGMT2_ADCENL);
@ -297,7 +297,7 @@ void audiohw_enable_recording(bool source_mic)
| ROUTMIX_BYPR2RMIX | ROUTMIX_DACR2RMIX); | ROUTMIX_BYPR2RMIX | ROUTMIX_DACR2RMIX);
} }
void audiohw_disable_recording(void) void audiohw_disable_recording(void)
{ {
wmcodec_write(LOUTMIX, LOUTMIX_DACL2LMIX); wmcodec_write(LOUTMIX, LOUTMIX_DACL2LMIX);
wmcodec_write(ROUTMIX, ROUTMIX_DACR2RMIX); wmcodec_write(ROUTMIX, ROUTMIX_DACR2RMIX);
@ -323,8 +323,7 @@ void audiohw_set_recvol(int left, int right, int type)
} }
} }
void audiohw_set_monitor(bool enable) void audiohw_set_monitor(bool enable)
{ {
(void)enable; (void)enable;
} }

179
firmware/export/wm8758.h
View file

@ -39,20 +39,19 @@ extern void audiohw_enable_lineout(bool enable);
#define RESET 0x00 #define RESET 0x00
#define RESET_RESET 0x0 #define RESET_RESET 0x0
#define PWRMGMT1 0x01 #define PWRMGMT1 0x01 /* default 000 */
#define PWRMGMT1_VMIDSEL_OFF (0 << 0) #define PWRMGMT1_VMIDSEL_OFF (0 << 0)
#define PWRMGMT1_VMIDSEL_75K (1 << 0) #define PWRMGMT1_VMIDSEL_100K (1 << 0)
#define PWRMGMT1_VMIDSEL_300K (2 << 0) #define PWRMGMT1_VMIDSEL_500K (2 << 0)
#define PWRMGMT1_VMIDSEL_5K (3 << 0) #define PWRMGMT1_VMIDSEL_10K (3 << 0)
#define PWRMGMT1_BUFIOEN (1 << 2) #define PWRMGMT1_BUFIOEN (1 << 2)
#define PWRMGMT1_BIASEN (1 << 3) #define PWRMGMT1_BIASEN (1 << 3)
#define PWRMGMT1_MICBEN (1 << 4) #define PWRMGMT1_MICBEN (1 << 4)
#define PWRMGMT1_PLLEN (1 << 5) #define PWRMGMT1_PLLEN (1 << 5)
#define PWRMGMT1_OUT3MIXEN (1 << 6) #define PWRMGMT1_OUT3MIXEN (1 << 6)
#define PWRMGMT1_OUT4MIXEN (1 << 7) #define PWRMGMT1_OUT4MIXEN (1 << 7)
#define PWRMGMT1_BUFDCOPEN (1 << 8)
#define PWRMGMT2 0x02 #define PWRMGMT2 0x02 /* default 000 */
#define PWRMGMT2_ADCENL (1 << 0) #define PWRMGMT2_ADCENL (1 << 0)
#define PWRMGMT2_ADCENR (1 << 1) #define PWRMGMT2_ADCENR (1 << 1)
#define PWRMGMT2_INPGAENL (1 << 2) #define PWRMGMT2_INPGAENL (1 << 2)
@ -63,7 +62,7 @@ extern void audiohw_enable_lineout(bool enable);
#define PWRMGMT2_LOUT1EN (1 << 7) #define PWRMGMT2_LOUT1EN (1 << 7)
#define PWRMGMT2_ROUT1EN (1 << 8) #define PWRMGMT2_ROUT1EN (1 << 8)
#define PWRMGMT3 0x03 #define PWRMGMT3 0x03 /* default 000 */
#define PWRMGMT3_DACENL (1 << 0) #define PWRMGMT3_DACENL (1 << 0)
#define PWRMGMT3_DACENR (1 << 1) #define PWRMGMT3_DACENR (1 << 1)
#define PWRMGMT3_LMIXEN (1 << 2) #define PWRMGMT3_LMIXEN (1 << 2)
@ -73,26 +72,26 @@ extern void audiohw_enable_lineout(bool enable);
#define PWRMGMT3_OUT3EN (1 << 7) #define PWRMGMT3_OUT3EN (1 << 7)
#define PWRMGMT3_OUT4EN (1 << 8) #define PWRMGMT3_OUT4EN (1 << 8)
#define AINTFCE 0x04 #define AINTFCE 0x04 /* default 050 */
#define AINTFCE_MONO (1 << 0) #define AINTFCE_MONO (1 << 0)
#define AINTFCE_ALRSWAP (1 << 1) #define AINTFCE_ALRSWAP (1 << 1)
#define AINTFCE_DLRSWAP (1 << 2) #define AINTFCE_DLRSWAP (1 << 2)
#define AINTFCE_FORMAT_MSB_RJUST (0 << 3) #define AINTFCE_FORMAT_MSB_RJUST (0 << 3)
#define AINTFCE_FORMAT_MSB_LJUST (1 << 3) #define AINTFCE_FORMAT_MSB_LJUST (1 << 3)
#define AINTFCE_FORMAT_I2S (2 << 3) #define AINTFCE_FORMAT_I2S (2 << 3) /* default */
#define AINTFCE_FORMAT_DSP (3 << 3) #define AINTFCE_FORMAT_DSP (3 << 3)
#define AINTFCE_FORMAT_MASK (3 << 3) #define AINTFCE_FORMAT_MASK (3 << 3)
#define AINTFCE_IWL_16BIT (0 << 5) #define AINTFCE_IWL_16BIT (0 << 5)
#define AINTFCE_IWL_20BIT (1 << 5) #define AINTFCE_IWL_20BIT (1 << 5)
#define AINTFCE_IWL_24BIT (2 << 5) #define AINTFCE_IWL_24BIT (2 << 5) /* default */
#define AINTFCE_IWL_32BIT (3 << 5) #define AINTFCE_IWL_32BIT (3 << 5)
#define AINTFCE_IWL_MASK (3 << 5) #define AINTFCE_IWL_MASK (3 << 5)
#define AINTFCE_LRP (1 << 7) #define AINTFCE_LRP (1 << 7)
#define AINTFCE_BCP (1 << 8) #define AINTFCE_BCP (1 << 8)
#define COMPCTRL 0x05 /* unused */ #define COMPCTRL 0x05 /* default 000 unused */
#define CLKCTRL 0x06 #define CLKCTRL 0x06 /* default 140 */
#define CLKCTRL_MS (1 << 0) #define CLKCTRL_MS (1 << 0)
#define CLKCTRL_BCLKDIV_1 (0 << 2) #define CLKCTRL_BCLKDIV_1 (0 << 2)
#define CLKCTRL_BCLKDIV_2 (1 << 2) #define CLKCTRL_BCLKDIV_2 (1 << 2)
@ -102,16 +101,16 @@ extern void audiohw_enable_lineout(bool enable);
#define CLKCTRL_BCLKDIV_32 (5 << 2) #define CLKCTRL_BCLKDIV_32 (5 << 2)
#define CLKCTRL_MCLKDIV_1 (0 << 5) #define CLKCTRL_MCLKDIV_1 (0 << 5)
#define CLKCTRL_MCLKDIV_1_5 (1 << 5) #define CLKCTRL_MCLKDIV_1_5 (1 << 5)
#define CLKCTRL_MCLKDIV_2 (2 << 5) #define CLKCTRL_MCLKDIV_2 (2 << 5) /* default */
#define CLKCTRL_MCLKDIV_3 (3 << 5) #define CLKCTRL_MCLKDIV_3 (3 << 5)
#define CLKCTRL_MCLKDIV_4 (4 << 5) #define CLKCTRL_MCLKDIV_4 (4 << 5)
#define CLKCTRL_MCLKDIV_6 (5 << 5) #define CLKCTRL_MCLKDIV_6 (5 << 5)
#define CLKCTRL_MCLKDIV_8 (6 << 5) #define CLKCTRL_MCLKDIV_8 (6 << 5)
#define CLKCTRL_MCLKDIV_12 (7 << 5) #define CLKCTRL_MCLKDIV_12 (7 << 5)
#define CLKCTRL_MCLKDIV_MASK (7 << 5) #define CLKCTRL_MCLKDIV_MASK (7 << 5)
#define CLKCTRL_CLKSEL (1 << 8) #define CLKCTRL_CLKSEL (1 << 8) /* default */
#define ADDCTRL 0x07 #define ADDCTRL 0x07 /* default 000 */
#define ADDCTRL_SLOWCLKEN (1 << 0) #define ADDCTRL_SLOWCLKEN (1 << 0)
#define ADDCTRL_SR_48kHz (0 << 1) #define ADDCTRL_SR_48kHz (0 << 1)
#define ADDCTRL_SR_32kHz (1 << 1) #define ADDCTRL_SR_32kHz (1 << 1)
@ -120,176 +119,194 @@ extern void audiohw_enable_lineout(bool enable);
#define ADDCTRL_SR_12kHz (4 << 1) #define ADDCTRL_SR_12kHz (4 << 1)
#define ADDCTRL_SR_8kHz (5 << 1) #define ADDCTRL_SR_8kHz (5 << 1)
#define ADDCTRL_SR_MASK (7 << 1) #define ADDCTRL_SR_MASK (7 << 1)
#define ADDCTRL_M128ENB (1 << 8)
/* unused */ #define GPIOCTRL 0x08 /* default 000 unused */
#define GPIOCTRL 0x08 #define JACKDETECTCTRL1 0x09 /* default 000 unused */
#define JACKDETECTCTRL1 0x09
#define DACCTRL 0x0a #define DACCTRL 0x0a /* default 000 */
#define DACCTRL_DACLPOL (1 << 0) #define DACCTRL_DACLPOL (1 << 0)
#define DACCTRL_DACRPOL (1 << 1) #define DACCTRL_DACRPOL (1 << 1)
#define DACCTRL_AMUTE (1 << 2) #define DACCTRL_AMUTE (1 << 2)
#define DACCTRL_DACOSR128 (1 << 3) #define DACCTRL_DACOSR128 (1 << 3)
#define DACCTRL_SOFTMUTE (1 << 6) #define DACCTRL_SOFTMUTE (1 << 6)
#define LDACVOL 0x0b #define LDACVOL 0x0b /* default 0ff */
#define LDACVOL_MASK 0xff #define LDACVOL_MASK 0xff
#define LDACVOL_DACVU (1 << 8) #define LDACVOL_DACVU (1 << 8)
#define RDACVOL 0x0c #define RDACVOL 0x0c /* default 0ff */
#define RDACVOL_MASK 0xff #define RDACVOL_MASK 0xff
#define RDACVOL_DACVU (1 << 8) #define RDACVOL_DACVU (1 << 8)
#define JACKDETECTCTRL2 0x0d /* unused */ #define JACKDETECTCTRL2 0x0d /* default 000 unused */
#define ADCCTRL 0x0e #define ADCCTRL 0x0e /* default 100 */
#define ADCCTRL_ADCLPOL (1 << 0) #define ADCCTRL_ADCLPOL (1 << 0)
#define ADCCTRL_ADCRPOL (1 << 1) #define ADCCTRL_ADCRPOL (1 << 1)
#define ADCCTRL_ADCOSR128 (1 << 3) #define ADCCTRL_ADCOSR128 (1 << 3)
#define ADCCTRL_HPFCUT_MASK (7 << 4) #define ADCCTRL_HPFCUT_MASK (7 << 4)
#define ADCCTRL_HPFAPP (1 << 7) #define ADCCTRL_HPFAPP (1 << 7)
#define ADCCTRL_HPFEN (1 << 8) #define ADCCTRL_HPFEN (1 << 8) /* default */
#define LADCVOL 0x0f #define LADCVOL 0x0f /* default 0ff */
#define LADCVOL_MASK 0xff #define LADCVOL_MASK 0xff
#define LADCVOL_ADCVU (1 << 8) #define LADCVOL_ADCVU (1 << 8)
#define RADCVOL 0x10 #define RADCVOL 0x10 /* default 0ff */
#define RADCVOL_MASK 0xff #define RADCVOL_MASK 0xff
#define RADCVOL_ADCVU (1 << 8) #define RADCVOL_ADCVU (1 << 8)
#define EQ1 0x12 #define EQ1 0x12 /* default 12c */
#define EQ5 0x16 #define EQ2 0x13 /* default 02c */
/* note: the WM8983 used for reference has a true 5 band EQ, but the WM8758 #define EQ3 0x14 /* default 02c */
* does only have low shelf & high shelf (tested). Not sure about 3D mode. */ #define EQ4 0x15 /* default 02c */
#define EQ1_EQ3DMODE (1 << 8) #define EQ5 0x16 /* default 02c */
/* note: WM8758 curruently runs on low power mode. 3 peaking filters
* and 3D will work when M128ENB is enabled + proper code. */
#define EQ1_EQ3DMODE (1 << 8) /* default */
#define EQ_GAIN_MASK 0x1f #define EQ_GAIN_MASK 0x1f
#define EQ_CUTOFF_MASK (3 << 5) #define EQ_CUTOFF_MASK (3 << 5)
#define EQ_GAIN_VALUE(x) (((-x) + 12) & 0x1f) #define EQ_GAIN_VALUE(x) (((-x) + 12) & 0x1f)
#define EQ_CUTOFF_VALUE(x) ((((x) - 1) & 0x03) << 5) #define EQ_CUTOFF_VALUE(x) ((((x) - 1) & 0x03) << 5)
/* unused */ #define DACLIMITER1 0x18 /* default 032 unused */
#define DACLIMITER1 0x18 #define DACLIMITER2 0x19 /* default 000 unused */
#define DACLIMITER2 0x19 #define NOTCHFILTER1 0x1b /* default 000 unused */
#define NOTCHFILTER1 0x1b #define NOTCHFILTER2 0x1c /* default 000 unused */
#define NOTCHFILTER2 0x1c #define NOTCHFILTER3 0x1d /* default 000 unused */
#define NOTCHFILTER3 0x1d #define NOTCHFILTER4 0x1e /* default 000 unused */
#define NOTCHFILTER4 0x1e #define ALCCONTROL1 0x20 /* default 038 unused */
#define ALCCONTROL1 0x20 #define ALCCONTROL2 0x21 /* default 00b unused */
#define ALCCONTROL2 0x21 #define ALCCONTROL3 0x22 /* default 032 unused */
#define ALCCONTROL3 0x22 #define NOISEGATE 0x23 /* default 000 unused */
#define NOISEGATE 0x23
#define PLLN 0x24 #define PLLN 0x24 /* default 008 */
#define PLLN_PLLN_MASK 0x0f #define PLLN_PLLN_MASK 0x0f
#define PLLN_PLLPRESCALE (1 << 4) #define PLLN_PLLPRESCALE (1 << 4)
#define PLLK1 0x25 #define PLLK1 0x25 /* default 00c */
#define PLLK1_MASK 0x3f #define PLLK1_MASK 0x3f
#define PLLK2 0x26 #define PLLK2 0x26 /* default 093 */
#define PLLK3 0x27 #define PLLK3 0x27 /* default 0e9 */
#define THREEDCTRL 0x29 #define THREEDCTRL 0x29 /* default 000 */
#define THREEDCTRL_DEPTH3D_MASK 0x0f #define THREEDCTRL_DEPTH3D_MASK 0x0f
#define OUT4TOADC 0x2a #define OUT4TOADC 0x2a /* default 000 */
#define OUT4TOADC_OUT1DEL (1 << 0) #define OUT4TOADC_OUT1DEL (1 << 0)
#define OUT4TOADC_DELEN (1 << 1) #define OUT4TOADC_DELEN (1 << 1)
#define OUT4TOADC_POBCTRL (1 << 2) #define OUT4TOADC_POBCTRL (1 << 2)
#define OUT4TOADC_OUT2DEL (1 << 3)
#define OUT4TOADC_VMIDTOG (1 << 4)
#define OUT4TOADC_OUT4_2LNR (1 << 5) #define OUT4TOADC_OUT4_2LNR (1 << 5)
#define OUT4TOADC_OUT4_ADCVOL_MASK (7 << 6) #define OUT4TOADC_OUT4_ADCVOL_MASK (7 << 6)
#define BEEPCTRL 0x2b #define BEEPCTRL 0x2b /* default 000 */
#define BEEPCTRL_BEEPEN (1 << 0) #define BEEPCTRL_DELEN2 (1 << 2)
#define BEEPCTRL_BEEPVOL_MASK (7 << 1)
#define BEEPCTRL_INVROUT2 (1 << 4)
#define BEEPCTRL_MUTERPGA2INV (1 << 5)
#define BEEPCTRL_BYPR2LMIX (1 << 7) #define BEEPCTRL_BYPR2LMIX (1 << 7)
#define BEEPCTRL_BYPL2RMIX (1 << 8) #define BEEPCTRL_BYPL2RMIX (1 << 8)
#define INCTRL 0x2c #define INCTRL 0x2c /* default 003 */
#define INCTRL_LIP2INPGA (1 << 0) #define INCTRL_LIP2INPGA (1 << 0) /* default */
#define INCTRL_LIN2INPGA (1 << 1) #define INCTRL_LIN2INPGA (1 << 1) /* default */
#define INCTRL_L2_2INPGA (1 << 2) #define INCTRL_L2_2INPGA (1 << 2)
#define INCTRL_RIP2INPGA (1 << 4) #define INCTRL_RIP2INPGA (1 << 4)
#define INCTRL_RIN2INPGA (1 << 5) #define INCTRL_RIN2INPGA (1 << 5)
#define INCTRL_R2_2INPGA (1 << 6) #define INCTRL_R2_2INPGA (1 << 6)
#define INCTRL_MBVSEL (1 << 8) #define INCTRL_MBVSEL (1 << 8)
#define LINPGAVOL 0x2d #define LINPGAVOL 0x2d /* default 010 */
#define LINPGAVOL_INPGAVOL_MASK 0x3f #define LINPGAVOL_INPGAVOL_MASK 0x3f
#define LINPGAVOL_INPGAMUTEL (1 << 6) #define LINPGAVOL_INPGAMUTEL (1 << 6)
#define LINPGAVOL_INPGAZCL (1 << 7) #define LINPGAVOL_INPGAZCL (1 << 7)
#define LINPGAVOL_INPGAVU (1 << 8) #define LINPGAVOL_INPGAVU (1 << 8)
#define RINPGAVOL 0x2e #define RINPGAVOL 0x2e /* default 010 */
#define RINPGAVOL_INPGAVOL_MASK 0x3f #define RINPGAVOL_INPGAVOL_MASK 0x3f
#define RINPGAVOL_INPGAMUTER (1 << 6) #define RINPGAVOL_INPGAMUTER (1 << 6)
#define RINPGAVOL_INPGAZCR (1 << 7) #define RINPGAVOL_INPGAZCR (1 << 7)
#define RINPGAVOL_INPGAVU (1 << 8) #define RINPGAVOL_INPGAVU (1 << 8)
#define LADCBOOST 0x2f #define LADCBOOST 0x2f /* default 100 */
#define LADCBOOST_AUXL2BOOST_MASK (7 << 0)
#define LADCBOOST_L2_2BOOST_MASK (7 << 4) #define LADCBOOST_L2_2BOOST_MASK (7 << 4)
#define LADCBOOST_L2_2BOOST(x) ((x) << 4) #define LADCBOOST_L2_2BOOST(x) ((x) << 4)
#define LADCBOOST_PGABOOSTL (1 << 8) #define LADCBOOST_PGABOOSTL (1 << 8) /* default */
#define RADCBOOST 0x30 #define RADCBOOST 0x30 /* default 100 */
#define RADCBOOST_AUXR2BOOST_MASK (7 << 0)
#define RADCBOOST_R2_2BOOST_MASK (7 << 4) #define RADCBOOST_R2_2BOOST_MASK (7 << 4)
#define RADCBOOST_R2_2BOOST(x) ((x) << 4) #define RADCBOOST_R2_2BOOST(x) ((x) << 4)
#define RADCBOOST_PGABOOSTR (1 << 8) #define RADCBOOST_PGABOOSTR (1 << 8) /* default */
#define OUTCTRL 0x31 #define OUTCTRL 0x31 /* default 002 */
#define OUTCTRL_VROI (1 << 0) #define OUTCTRL_VROI (1 << 0)
#define OUTCTRL_TSDEN (1 << 1) #define OUTCTRL_TSDEN (1 << 1) /* default */
#define OUTCTRL_SPKBOOST (1 << 2) #define OUTCTRL_TSOPCTRL (1 << 2)
#define OUTCTRL_OUT3BOOST (1 << 3) #define OUTCTRL_OUT3ENDEL (1 << 3)
#define OUTCTRL_OUT4BOOST (1 << 4) #define OUTCTRL_OUT4ENDEL (1 << 4)
#define OUTCTRL_DACR2LMIX (1 << 5) #define OUTCTRL_DACR2LMIX (1 << 5)
#define OUTCTRL_DACL2RMIX (1 << 6) #define OUTCTRL_DACL2RMIX (1 << 6)
#define OUTCTRL_LINE_COM (1 << 7)
#define OUTCTRL_HP_COM (1 << 8)
#define LOUTMIX 0x32 #define LOUTMIX 0x32 /* default 001 */
#define LOUTMIX_DACL2LMIX (1 << 0) #define LOUTMIX_DACL2LMIX (1 << 0) /* default */
#define LOUTMIX_BYPL2LMIX (1 << 1) #define LOUTMIX_BYPL2LMIX (1 << 1)
#define LOUTMIX_BYP2LMIXVOL_MASK (7 << 2) #define LOUTMIX_BYP2LMIXVOL_MASK (7 << 2)
#define LOUTMIX_BYP2LMIXVOL(x) ((x) << 2) #define LOUTMIX_BYP2LMIXVOL(x) ((x) << 2)
#define LOUTMIX_AUXL2LMIX (1 << 5)
#define LOUTMIX_AUXLMIXVOL_MASK (7 << 6)
#define ROUTMIX 0x33 #define ROUTMIX 0x33 /* default 001 */
#define ROUTMIX_DACR2RMIX (1 << 0) #define ROUTMIX_DACR2RMIX (1 << 0) /* default */
#define ROUTMIX_BYPR2RMIX (1 << 1) #define ROUTMIX_BYPR2RMIX (1 << 1)
#define ROUTMIX_BYP2RMIXVOL_MASK (7 << 2) #define ROUTMIX_BYP2RMIXVOL_MASK (7 << 2)
#define ROUTMIX_BYP2RMIXVOL(x) ((x) << 2) #define ROUTMIX_BYP2RMIXVOL(x) ((x) << 2)
#define ROUTMIX_AUXR2RMIX (1 << 5)
#define ROUTMIX_AUXRMIXVOL_MASK (7 << 6)
#define LOUT1VOL 0x34 #define LOUT1VOL 0x34 /* default 039 */
#define LOUT1VOL_MASK 0x3f #define LOUT1VOL_MASK 0x3f
#define LOUT1VOL_LOUT1MUTE (1 << 6) #define LOUT1VOL_LOUT1MUTE (1 << 6)
#define LOUT1VOL_LOUT1ZC (1 << 7) #define LOUT1VOL_LOUT1ZC (1 << 7)
#define LOUT1VOL_OUT1VU (1 << 8) #define LOUT1VOL_OUT1VU (1 << 8)
#define ROUT1VOL 0x35 #define ROUT1VOL 0x35 /* default 039 */
#define ROUT1VOL_MASK 0x3f #define ROUT1VOL_MASK 0x3f
#define ROUT1VOL_ROUT1MUTE (1 << 6) #define ROUT1VOL_ROUT1MUTE (1 << 6)
#define ROUT1VOL_ROUT1ZC (1 << 7) #define ROUT1VOL_ROUT1ZC (1 << 7)
#define ROUT1VOL_OUT1VU (1 << 8) #define ROUT1VOL_OUT1VU (1 << 8)
#define LOUT2VOL 0x36 #define LOUT2VOL 0x36 /* default 039 */
#define LOUT2VOL_MASK 0x3f #define LOUT2VOL_MASK 0x3f
#define LOUT2VOL_LOUT2MUTE (1 << 6) #define LOUT2VOL_LOUT2MUTE (1 << 6)
#define LOUT2VOL_LOUT2ZC (1 << 7) #define LOUT2VOL_LOUT2ZC (1 << 7)
#define LOUT2VOL_OUT2VU (1 << 8) #define LOUT2VOL_OUT2VU (1 << 8)
#define ROUT2VOL 0x37 #define ROUT2VOL 0x37 /* default 039 */
#define ROUT2VOL_MASK 0x3f #define ROUT2VOL_MASK 0x3f
#define ROUT2VOL_ROUT2MUTE (1 << 6) #define ROUT2VOL_ROUT2MUTE (1 << 6)
#define ROUT2VOL_ROUT2ZC (1 << 7) #define ROUT2VOL_ROUT2ZC (1 << 7)
#define ROUT2VOL_OUT2VU (1 << 8) #define ROUT2VOL_OUT2VU (1 << 8)
#define OUT3MIX 0x38 /* default 001 */
#define OUT3MIX_LDAC2OUT3 (1 << 0) /* default */
#define OUT3MIX_LMIX2OUT3 (1 << 1)
#define OUT3MIX_BYPL2OUT3 (1 << 2)
#define OUT3MIX_OUT4_2OUT3 (1 << 3)
#define OUT3MIX_OUT3MUTE (1 << 6)
#define OUT4MIX 0x39 /* default 001 */
#define OUT4MIX_RDAC2OUT4 (1 << 0) /* default */
#define OUT4MIX_RMIX2OUT4 (1 << 1)
#define OUT4MIX_BYPR2OUT4 (1 << 2)
#define OUT4MIX_LDAC2OUT4 (1 << 3)
#define OUT4MIX_LMIX2OUT4 (1 << 4)
#define OUT4MIX_OUT4ATTN (1 << 5)
#define OUT4MIX_OUT4MUTE (1 << 6)
#define OUT4MIX_OUT3_2OUT4 (1 << 7)
#define BIASCTRL 0x3d /* default 000 */
#define BIASCTRL_HALFOPBIAS (1 << 0)
#define BIASCTRL_HALFI_IPGA (1 << 6)
#define BIASCTRL_BIASCUT (1 << 8)
/* Dummy definition, to be removed when the audio driver API gets reworked. */ /* Dummy definition, to be removed when the audio driver API gets reworked. */
#define WM8758_44100HZ 0 #define WM8758_44100HZ 0