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Change alignment macros to allow further performance optimization. Define the CACHEALIGN macros for all ARM CPUs, the used alignment size is derived from CACHEALIGN_BITS which has been defined for each supported ARM CPU with r28619. The default alignment size for ARM is set to 32 bytes as new -- not yet supported -- ARM CPUs will most probably need this alignment. To be able to differ between ARM and other CPUs a new macro called MEM_ALIGN_ATTR is introduced. This equals CACHEALIGN_ATTR for ARM, 16 byte alignment for Coldfire and is kept empty for other CPUs. MEM_ALIGN_ATTR is available system wide. From measurements it is expected that the usage of MEM_ALIGN_ATTR can give significant performance gain on ARM11 CPUs.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28625 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Andree Buschmann 2010-11-21 12:27:01 +00:00
parent f54cbfa164
commit eef21cb18a
2 changed files with 64 additions and 49 deletions
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4
firmware/target/arm/system-target.h
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@ -158,10 +158,6 @@ static inline void wake_core(int core)
((typeof (a))((uintptr_t)(a) | UNCACHED_BASE_ADDR))
#endif /* BOOTLOADER */
/* Certain data needs to be out of the way of cache line interference
* such as data for COP use or for use with UNCACHED_ADDR */
#define PROC_NEEDS_CACHEALIGN
#if defined(CPU_PP502x) && defined(HAVE_ATA_DMA)
#define STORAGE_WANTS_ALIGN
#endif