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Sansa AMS: VIC_INT_ENABLE register is not a mask
When read it returns all enabled interrupt sources When written it enables interrupt sources for each bit set So just like VIC_INT_EN_CLEAR, we don't have to read the previous value before writing to it (VIC_INT_EN_CLEAR is write-only anyway) Thanks to Fred Bauer for spotting git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23734 a1c6a512-1295-4272-9138-f99709370657
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6 changed files with 10 additions and 10 deletions
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@ -456,11 +456,11 @@ static void init_pl180_controller(const int drive)
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MCI_MASK0(drive) = MCI_ERROR | MCI_DATA_END;
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MCI_MASK0(drive) = MCI_ERROR | MCI_DATA_END;
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MCI_MASK1(drive) = 0;
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MCI_MASK1(drive) = 0;
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#ifdef HAVE_MULTIDRIVE
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#ifdef HAVE_MULTIDRIVE
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VIC_INT_ENABLE |=
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VIC_INT_ENABLE =
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(drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
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(drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
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/* setup isr for microsd monitoring */
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/* setup isr for microsd monitoring */
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VIC_INT_ENABLE |= (INTERRUPT_GPIOA);
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VIC_INT_ENABLE = (INTERRUPT_GPIOA);
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/* clear previous irq */
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/* clear previous irq */
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GPIOA_IC = (1<<2);
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GPIOA_IC = (1<<2);
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/* enable edge detecting */
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/* enable edge detecting */
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@ -469,7 +469,7 @@ static void init_pl180_controller(const int drive)
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GPIOA_IBE |= (1<<2);
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GPIOA_IBE |= (1<<2);
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#else
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#else
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VIC_INT_ENABLE |= INTERRUPT_NAND;
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VIC_INT_ENABLE = INTERRUPT_NAND;
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#endif
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#endif
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MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0); /* OF Setting */
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MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0); /* OF Setting */
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@ -49,7 +49,7 @@ void dma_release(void)
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void dma_init(void)
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void dma_init(void)
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{
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{
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DMAC_SYNC = 0xffff; /* disable synchronisation logic */
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DMAC_SYNC = 0xffff; /* disable synchronisation logic */
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VIC_INT_ENABLE |= INTERRUPT_DMAC;
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VIC_INT_ENABLE = INTERRUPT_DMAC;
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}
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}
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inline void dma_disable_channel(int channel)
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inline void dma_disable_channel(int channel)
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@ -64,7 +64,7 @@ void tick_start(unsigned int interval_in_ms)
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int cycles = KERNEL_TIMER_FREQ / 1000 * interval_in_ms;
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int cycles = KERNEL_TIMER_FREQ / 1000 * interval_in_ms;
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CGU_PERI |= CGU_TIMER2_CLOCK_ENABLE; /* enable peripheral */
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CGU_PERI |= CGU_TIMER2_CLOCK_ENABLE; /* enable peripheral */
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VIC_INT_ENABLE |= INTERRUPT_TIMER2; /* enable interrupt */
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VIC_INT_ENABLE = INTERRUPT_TIMER2; /* enable interrupt */
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TIMER2_LOAD = TIMER2_BGLOAD = cycles; /* timer period */
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TIMER2_LOAD = TIMER2_BGLOAD = cycles; /* timer period */
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@ -51,7 +51,7 @@ void pcm_play_lock(void)
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void pcm_play_unlock(void)
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void pcm_play_unlock(void)
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{
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{
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if(--locked == 0)
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if(--locked == 0)
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VIC_INT_ENABLE |= INTERRUPT_DMAC;
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VIC_INT_ENABLE = INTERRUPT_DMAC;
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}
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}
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static void play_start_pcm(void)
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static void play_start_pcm(void)
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@ -196,7 +196,7 @@ void pcm_rec_lock(void)
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void pcm_rec_unlock(void)
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void pcm_rec_unlock(void)
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{
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{
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if(--rec_locked == 0)
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if(--rec_locked == 0)
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VIC_INT_ENABLE |= INTERRUPT_I2SIN;
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VIC_INT_ENABLE = INTERRUPT_I2SIN;
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}
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}
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@ -275,7 +275,7 @@ void pcm_rec_dma_start(void *addr, size_t size)
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I2SIN_MASK = (1<<6) | (1<<0) |
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I2SIN_MASK = (1<<6) | (1<<0) |
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(1<<3) | (1<<2) | (1<<1); /* half full, almost full, full */
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(1<<3) | (1<<2) | (1<<1); /* half full, almost full, full */
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VIC_INT_ENABLE |= INTERRUPT_I2SIN;
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VIC_INT_ENABLE = INTERRUPT_I2SIN;
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}
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}
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@ -56,7 +56,7 @@ bool timer_set(long cycles, bool start)
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bool timer_start(void)
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bool timer_start(void)
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{
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{
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CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */
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CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */
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VIC_INT_ENABLE |= INTERRUPT_TIMER1;
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VIC_INT_ENABLE = INTERRUPT_TIMER1;
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return true;
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return true;
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}
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}
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@ -187,7 +187,7 @@ void usb_drv_init(void)
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USB_DEV_EP_INTR_MASK &= ~((1<<0) | (1<<16)); /* ep 0 */
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USB_DEV_EP_INTR_MASK &= ~((1<<0) | (1<<16)); /* ep 0 */
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VIC_INT_ENABLE |= INTERRUPT_USB;
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VIC_INT_ENABLE = INTERRUPT_USB;
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USB_IEP_CTRL(0) |= (1<<7); /* set NAK */
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USB_IEP_CTRL(0) |= (1<<7); /* set NAK */
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USB_OEP_CTRL(0) |= (1<<7); /* set NAK */
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USB_OEP_CTRL(0) |= (1<<7); /* set NAK */
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