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Reclaim .iram areas in DRAM by overlapping their load addresses with the uninitialized data sections. I did what I could test out-- not any flash image linker scripts or other target processors. Move any .iram copies in crt0.S's to be the first operation even if not _strictly_ necessary to be emphatic (aka. 'beware').
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20061 a1c6a512-1295-4272-9138-f99709370657
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parent
07ae1e4fb9
commit
ec67912b63
11 changed files with 76 additions and 65 deletions
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@ -41,7 +41,6 @@ start:
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.equ COP_CTRL, 0xcf004058
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.equ CPU_STATUS, 0xcf004050
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.equ COP_STATUS, 0xcf004050
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.equ IIS_CONFIG, 0xc0002500
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.equ SLEEP, 0x000000ca
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.equ WAKE, 0x000000ce
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.equ CPUSLEEPING, 0x00008000
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@ -63,7 +62,6 @@ start:
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.equ COP_ICLR, 0x60004038
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.equ COP_CTRL, 0x60007004
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.equ COP_STATUS, 0x60007004
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.equ IIS_CONFIG, 0x70002800
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.equ SLEEP, 0x80000000
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.equ WAKE, 0x00000000
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.equ CPUSLEEPING, 0x80000000
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@ -186,6 +184,9 @@ cpu_init:
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ldr r3, [r4]
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tst r3, #COPSLEEPING
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beq 1b
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/* Vectors and IRAM copy is done first since they are reclaimed for
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* other uninitialized sections */
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/* Copy exception handler code to address 0 */
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ldr r2, =_vectorsstart
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@ -196,16 +197,7 @@ cpu_init:
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Copy the IRAM */
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ldr r2, =_iramcopy
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ldr r3, =_iramstart
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@ -216,6 +208,15 @@ cpu_init:
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strhi r5, [r3], #4
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bhi 1b
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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@ -103,6 +103,7 @@ SECTIONS
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} AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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_noloaddram = LOADADDR(.vectors);
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.ibss IRAMORIG (NOLOAD) :
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{
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@ -148,8 +149,7 @@ SECTIONS
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/* .bss and .ncbss are treated as a single section to use one init loop to
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* zero it - note "_edata" and "_end" */
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
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SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
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.bss _noloaddram (NOLOAD) :
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{
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_edata = .;
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*(.bss*)
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@ -103,6 +103,7 @@ SECTIONS
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} AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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_noloaddram = LOADADDR(.vectors);
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.ibss IRAMORIG (NOLOAD) :
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{
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@ -148,8 +149,7 @@ SECTIONS
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/* .bss and .ncbss are treated as a single section to use one init loop to
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* zero it - note "_edata" and "_end" */
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
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SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
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.bss _noloaddram (NOLOAD) :
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{
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_edata = .;
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*(.bss*)
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@ -103,6 +103,7 @@ SECTIONS
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} AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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_noloaddram = LOADADDR(.vectors);
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.ibss IRAMORIG (NOLOAD) :
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{
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@ -148,8 +149,7 @@ SECTIONS
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/* .bss and .ncbss are treated as a single section to use one init loop to
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* zero it - note "_edata" and "_end" */
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
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SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
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.bss _noloaddram (NOLOAD) :
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{
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_edata = .;
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*(.bss*)
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@ -103,6 +103,7 @@ SECTIONS
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} AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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_noloaddram = LOADADDR(.vectors);
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.ibss IRAMORIG (NOLOAD) :
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{
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@ -148,8 +149,7 @@ SECTIONS
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/* .bss and .ncbss are treated as a single section to use one init loop to
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* zero it - note "_edata" and "_end" */
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
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SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
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.bss _noloaddram (NOLOAD) :
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{
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_edata = .;
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*(.bss*)
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@ -103,6 +103,7 @@ SECTIONS
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} AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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_noloaddram = LOADADDR(.vectors);
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.ibss IRAMORIG (NOLOAD) :
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{
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@ -145,11 +146,10 @@ SECTIONS
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. += 0x2000;
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stackend = .;
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} > IRAM
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/* .bss and .ncbss are treated as a single section to use one init loop to
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* zero it - note "_edata" and "_end" */
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
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SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
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.bss _noloaddram (NOLOAD) :
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{
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_edata = .;
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*(.bss*)
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