mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-11-09 13:12:37 -05:00
More exodus to the target tree for ColdFire and a bonus sorting of firmware/SOURCES.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11468 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
f9c8a891af
commit
e89a3940f9
8 changed files with 396 additions and 464 deletions
241
firmware/target/coldfire/i2c-coldfire.c
Normal file
241
firmware/target/coldfire/i2c-coldfire.c
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@ -0,0 +1,241 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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* $Id$
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*
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* Copyright (C) 2005 by Andy Young
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "cpu.h"
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#include "kernel.h"
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#include "logf.h"
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#include "system.h"
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#include "i2c-coldfire.h"
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/* --- Local functions - declarations --- */
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static int i2c_start(volatile unsigned char *iface);
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static int i2c_wait_for_slave(volatile unsigned char *iface);
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static int i2c_outb(volatile unsigned char *iface, unsigned char byte);
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inline void i2c_stop(volatile unsigned char *iface);
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/* --- Public functions - implementation --- */
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void i2c_init(void)
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{
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#ifdef IRIVER_H100_SERIES
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/* The FM chip has no pullup for SCL, so we have to bit-bang the
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I2C for that one. */
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or_l(0x00800000, &GPIO1_OUT);
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or_l(0x00000008, &GPIO_OUT);
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or_l(0x00800000, &GPIO1_ENABLE);
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or_l(0x00000008, &GPIO_ENABLE);
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or_l(0x00800000, &GPIO1_FUNCTION);
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or_l(0x00000008, &GPIO_FUNCTION);
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#elif defined(IRIVER_H300_SERIES)
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/* The FM chip has no pullup for SCL, so we have to bit-bang the
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I2C for that one. */
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or_l(0x03000000, &GPIO1_OUT);
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or_l(0x03000000, &GPIO1_ENABLE);
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or_l(0x03000000, &GPIO1_FUNCTION);
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#endif
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/* I2C Clock divisor = 160 => 124.1556 MHz / 2 / 160 = 388.08 kHz */
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MFDR = 0x0d;
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MFDR2 = 0x0d;
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#ifdef IAUDIO_X5
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MBCR = IEN; /* Enable interface */
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MBCR2 = IEN;
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#endif
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#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES)
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/* Audio Codec */
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MBDR = 0; /* iRiver firmware does this */
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MBCR = IEN; /* Enable interface */
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#endif
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}
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void i2c_close(void)
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{
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MBCR = 0;
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MBCR2 = 0;
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}
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/*
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* Writes bytes to a I2C device.
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*
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* Returns number of bytes successfully sent or a negative value on error.
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*/
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int i2c_write(volatile unsigned char *iface, unsigned char addr,
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const unsigned char *buf, int count)
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{
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int i, rc;
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if ( ! count)
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return 0;
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rc = i2c_start(iface);
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if (rc < 0)
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return rc;
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rc = i2c_outb(iface, addr & 0xfe);
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if (rc < 0)
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return rc;
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for (i = 0; i < count; i++)
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{
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rc = i2c_outb(iface, *buf++);
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if (rc < 0)
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return rc;
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}
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i2c_stop(iface);
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return count;
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}
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/*
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* Reads bytes from a I2C device.
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*
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* Returns number of bytes successfully received or a negative value on error.
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*/
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int i2c_read(volatile unsigned char *iface, unsigned char addr,
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unsigned char *buf, int count)
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{
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int i, rc;
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if ( ! count)
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return 0;
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rc = i2c_start(iface);
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if (rc < 0)
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return rc;
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rc = i2c_outb(iface, addr | 1);
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if (rc < 0)
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return rc;
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/* Switch to Rx mode */
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iface[O_MBCR] &= ~MTX;
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iface[O_MBCR] &= ~TXAK;
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/* Dummy read */
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rc = (int) iface[O_MBDR];
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for (i = 0; i < count; i++)
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{
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rc = i2c_wait_for_slave(iface);
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if (rc < 0)
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return rc;
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if (i == count-2)
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/* Don't ACK the next-to-last byte */
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iface[O_MBCR] |= TXAK;
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if (i == count-1)
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/* Generate STOP before reading last byte */
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i2c_stop(iface);
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*buf++ = iface[O_MBDR];
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}
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return count;
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}
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/* --- Local functions - implementation --- */
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/* Begin I2C session on the given interface.
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*
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* Returns 0 on success, negative value on error.
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*/
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int i2c_start(volatile unsigned char *iface)
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{
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/* Wait for bus to become free */
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int j = MAX_LOOP;
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while (--j && (iface[O_MBSR] & IBB))
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;
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if (!j)
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{
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logf("i2c: bus is busy (iface=%08x)", iface);
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return -1;
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}
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/* Generate START and prepare for write */
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iface[O_MBCR] |= (MSTA | TXAK | MTX);
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return 0;
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}
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/* Wait for slave to act on given I2C interface.
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*
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* Returns 0 on success, negative value on error.
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*/
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int i2c_wait_for_slave(volatile unsigned char *iface)
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{
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int j = MAX_LOOP;
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while (--j && ! (iface[O_MBSR] & IFF))
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;
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if (!j)
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{
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logf("i2c: IFF not set (iface=%08x)", iface);
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i2c_stop(iface);
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return -2;
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}
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/* Clear interrupt flag */
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iface[O_MBSR] &= ~IFF;
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return 0;
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}
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/* Write the given byte to the given I2C interface.
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*
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* Returns 0 on success, negative value on error.
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*/
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int i2c_outb(volatile unsigned char *iface, unsigned char byte)
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{
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int rc;
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iface[O_MBDR] = byte;
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rc = i2c_wait_for_slave(iface);
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if (rc < 0)
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return rc;
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/* Check that transfer is complete */
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if ( !(iface[O_MBSR] & ICF))
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{
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logf("i2c: transfer error (iface=%08x)", iface);
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i2c_stop(iface);
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return -3;
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}
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/* Check that the byte has been ACKed */
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if (iface[O_MBSR] & RXAK)
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{
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logf("i2c: no ACK (iface=%08x)", iface);
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i2c_stop(iface);
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return -4;
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}
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return 0;
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}
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/* End I2C session on the given interface. */
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inline void i2c_stop(volatile unsigned char *iface)
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{
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iface[O_MBCR] &= ~MSTA;
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}
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1298
firmware/target/coldfire/iriver/h100/lcd-h100.c
Normal file
1298
firmware/target/coldfire/iriver/h100/lcd-h100.c
Normal file
File diff suppressed because it is too large
Load diff
425
firmware/target/coldfire/iriver/h300/lcd-h300.c
Normal file
425
firmware/target/coldfire/iriver/h300/lcd-h300.c
Normal file
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@ -0,0 +1,425 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2004 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#include "lcd.h"
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#include "kernel.h"
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#include "thread.h"
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#include <string.h>
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#include <stdlib.h>
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#include "file.h"
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#include "debug.h"
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#include "system.h"
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#include "font.h"
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#include "bidi.h"
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static bool display_on = false; /* is the display turned on? */
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static bool display_flipped = false;
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static int xoffset = 0; /* needed for flip */
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/* register defines */
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#define R_START_OSC 0x00
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#define R_DRV_OUTPUT_CONTROL 0x01
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#define R_DRV_WAVEFORM_CONTROL 0x02
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#define R_ENTRY_MODE 0x03
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#define R_COMPARE_REG1 0x04
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#define R_COMPARE_REG2 0x05
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#define R_DISP_CONTROL1 0x07
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#define R_DISP_CONTROL2 0x08
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#define R_DISP_CONTROL3 0x09
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#define R_FRAME_CYCLE_CONTROL 0x0b
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#define R_EXT_DISP_IF_CONTROL 0x0c
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#define R_POWER_CONTROL1 0x10
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#define R_POWER_CONTROL2 0x11
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#define R_POWER_CONTROL3 0x12
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#define R_POWER_CONTROL4 0x13
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#define R_RAM_ADDR_SET 0x21
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#define R_WRITE_DATA_2_GRAM 0x22
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#define R_GAMMA_FINE_ADJ_POS1 0x30
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#define R_GAMMA_FINE_ADJ_POS2 0x31
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#define R_GAMMA_FINE_ADJ_POS3 0x32
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#define R_GAMMA_GRAD_ADJ_POS 0x33
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#define R_GAMMA_FINE_ADJ_NEG1 0x34
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#define R_GAMMA_FINE_ADJ_NEG2 0x35
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#define R_GAMMA_FINE_ADJ_NEG3 0x36
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#define R_GAMMA_GRAD_ADJ_NEG 0x37
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#define R_GAMMA_AMP_ADJ_RES_POS 0x38
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#define R_GAMMA_AMP_AVG_ADJ_RES_NEG 0x39
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#define R_GATE_SCAN_POS 0x40
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#define R_VERT_SCROLL_CONTROL 0x41
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#define R_1ST_SCR_DRV_POS 0x42
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#define R_2ND_SCR_DRV_POS 0x43
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#define R_HORIZ_RAM_ADDR_POS 0x44
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#define R_VERT_RAM_ADDR_POS 0x45
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#define LCD_CMD (*(volatile unsigned short *)0xf0000000)
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#define LCD_DATA (*(volatile unsigned short *)0xf0000002)
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/* called very frequently - inline! */
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static inline void lcd_write_reg(int reg, int val)
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{
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LCD_CMD = reg;
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LCD_DATA = val;
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}
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/* called very frequently - inline! */
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static inline void lcd_begin_write_gram(void)
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{
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LCD_CMD = R_WRITE_DATA_2_GRAM;
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}
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/*** hardware configuration ***/
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void lcd_set_contrast(int val)
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{
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(void)val;
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}
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void lcd_set_invert_display(bool yesno)
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{
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(void)yesno;
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}
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static void flip_lcd(bool yesno)
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{
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if (yesno)
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{
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lcd_write_reg(R_DRV_OUTPUT_CONTROL, 0x031b); /* 224 lines, GS=SS=1 */
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lcd_write_reg(R_GATE_SCAN_POS, 0x0002); /* 16 lines offset */
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lcd_write_reg(R_1ST_SCR_DRV_POS, 0xdf04); /* 4..223 */
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}
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else
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{
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lcd_write_reg(R_DRV_OUTPUT_CONTROL, 0x001b); /* 224 lines, GS=SS=0 */
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lcd_write_reg(R_GATE_SCAN_POS, 0x0000);
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lcd_write_reg(R_1ST_SCR_DRV_POS, 0xdb00); /* 0..219 */
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}
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}
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/* turn the display upside down (call lcd_update() afterwards) */
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void lcd_set_flip(bool yesno)
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{
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display_flipped = yesno;
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xoffset = yesno ? 4 : 0;
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if (display_on)
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flip_lcd(yesno);
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}
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static void _display_on(void)
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{
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/** Sequence according to datasheet, p. 132 **/
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lcd_write_reg(R_START_OSC, 0x0001); /* Start Oscilation */
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sleep(1);
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/* zero everything*/
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lcd_write_reg(R_POWER_CONTROL1, 0x0000); /* STB = 0, SLP = 0 */
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lcd_write_reg(R_DISP_CONTROL1, 0x0000); /* GON = 0, DTE = 0, D1-0 = 00b */
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lcd_write_reg(R_POWER_CONTROL3, 0x0000); /* PON = 0 */
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lcd_write_reg(R_POWER_CONTROL4, 0x0000); /* VCOMG = 0 */
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sleep(1);
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|
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/* initialise power supply */
|
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|
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/* DC12-10 = 000b: Step-up1 = clock/8,
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* DC02-00 = 000b: Step-up2 = clock/16,
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* VC2-0 = 010b: VciOUT = 0.87 * VciLVL */
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lcd_write_reg(R_POWER_CONTROL2, 0x0002);
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/* VRH3-0 = 1000b: Vreg1OUT = REGP * 1.90 */
|
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lcd_write_reg(R_POWER_CONTROL3, 0x0008);
|
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/* VDV4-0 = 00110b: VcomA = Vreg1OUT * 0.76,
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* VCM4-0 = 10000b: VcomH = Vreg1OUT * 0.70*/
|
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lcd_write_reg(R_POWER_CONTROL4, 0x0610);
|
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|
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lcd_write_reg(R_POWER_CONTROL1, 0x0044); /* AP2-0 = 100b, DK = 1 */
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lcd_write_reg(R_POWER_CONTROL3, 0x0018); /* PON = 1 */
|
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|
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sleep(4); /* Step-up circuit stabilising time */
|
||||
|
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/* start power supply */
|
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|
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lcd_write_reg(R_POWER_CONTROL1, 0x0540); /* BT2-0 = 101b, DK = 0 */
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lcd_write_reg(R_POWER_CONTROL4, 0x2610); /* VCOMG = 1 */
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||||
|
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/* other settings */
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|
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/* B/C = 1: n-line inversion form
|
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* EOR = 1: polarity inversion occurs by applying an EOR to odd/even
|
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* frame select signal and an n-line inversion signal.
|
||||
* FLD = 01b: 1 field interlaced scan, external display iface */
|
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lcd_write_reg(R_DRV_WAVEFORM_CONTROL, 0x0700);
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|
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/* Address counter updated in vertical direction; left to right;
|
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* vertical increment horizontal increment.
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* data format for 8bit transfer or spi = 65k (5,6,5)
|
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* Reverse order of RGB to BGR for 18bit data written to GRAM
|
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* Replace data on writing to GRAM */
|
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lcd_write_reg(R_ENTRY_MODE, 0x7038);
|
||||
|
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flip_lcd(display_flipped);
|
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|
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lcd_write_reg(R_2ND_SCR_DRV_POS, 0x0000);
|
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lcd_write_reg(R_VERT_SCROLL_CONTROL, 0x0000);
|
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|
||||
/* 19 clocks,no equalization */
|
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lcd_write_reg(R_FRAME_CYCLE_CONTROL, 0x0002);
|
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|
||||
/* Transfer mode for RGB interface disabled
|
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* internal clock operation;
|
||||
* System interface/VSYNC interface */
|
||||
lcd_write_reg(R_EXT_DISP_IF_CONTROL, 0x0003);
|
||||
|
||||
/* Front porch lines: 8; Back porch lines: 8; */
|
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lcd_write_reg(R_DISP_CONTROL2, 0x0808);
|
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|
||||
/* Scan mode by the gate driver in the non-display area: disabled;
|
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* Cycle of scan by the gate driver - set to 31frames(518ms),
|
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* disabled by above setting */
|
||||
lcd_write_reg(R_DISP_CONTROL3, 0x003f);
|
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|
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lcd_write_reg(R_GAMMA_FINE_ADJ_POS1, 0x0003);
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lcd_write_reg(R_GAMMA_FINE_ADJ_POS2, 0x0707);
|
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lcd_write_reg(R_GAMMA_FINE_ADJ_POS3, 0x0007);
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lcd_write_reg(R_GAMMA_GRAD_ADJ_POS, 0x0705);
|
||||
lcd_write_reg(R_GAMMA_FINE_ADJ_NEG1, 0x0007);
|
||||
lcd_write_reg(R_GAMMA_FINE_ADJ_NEG2, 0x0000);
|
||||
lcd_write_reg(R_GAMMA_FINE_ADJ_NEG3, 0x0407);
|
||||
lcd_write_reg(R_GAMMA_GRAD_ADJ_NEG, 0x0507);
|
||||
lcd_write_reg(R_GAMMA_AMP_ADJ_RES_POS, 0x1d09);
|
||||
lcd_write_reg(R_GAMMA_AMP_AVG_ADJ_RES_NEG, 0x0303);
|
||||
|
||||
display_on=true; /* must be done before calling lcd_update() */
|
||||
lcd_update();
|
||||
|
||||
sleep(4); /* op-amp stabilising time */
|
||||
|
||||
/** Sequence according to datasheet, p. 130 **/
|
||||
|
||||
lcd_write_reg(R_POWER_CONTROL1, 0x4540); /* SAP2-0=100, BT2-0=101, AP2-0=100 */
|
||||
lcd_write_reg(R_DISP_CONTROL1, 0x0005); /* GON=0, DTE=0, REV=1, D1-0=01 */
|
||||
sleep(2);
|
||||
|
||||
lcd_write_reg(R_DISP_CONTROL1, 0x0025); /* GON=1, DTE=0, REV=1, D1-0=01 */
|
||||
lcd_write_reg(R_DISP_CONTROL1, 0x0027); /* GON=1, DTE=0, REV=1, D1-0=11 */
|
||||
sleep(2);
|
||||
|
||||
lcd_write_reg(R_DISP_CONTROL1, 0x0037); /* GON=1, DTE=1, REV=1, D1-0=11 */
|
||||
}
|
||||
|
||||
/* LCD init */
|
||||
void lcd_init_device(void)
|
||||
{
|
||||
/* GPO46 is LCD RESET */
|
||||
or_l(0x00004000, &GPIO1_OUT);
|
||||
or_l(0x00004000, &GPIO1_ENABLE);
|
||||
or_l(0x00004000, &GPIO1_FUNCTION);
|
||||
|
||||
/* Reset LCD */
|
||||
and_l(~0x00004000, &GPIO1_OUT);
|
||||
sleep(1);
|
||||
or_l(0x00004000, &GPIO1_OUT);
|
||||
sleep(1);
|
||||
|
||||
_display_on();
|
||||
}
|
||||
|
||||
void lcd_enable(bool on)
|
||||
{
|
||||
if(display_on!=on)
|
||||
{
|
||||
if(on)
|
||||
{
|
||||
_display_on();
|
||||
}
|
||||
else
|
||||
{
|
||||
/** Off sequence according to datasheet, p. 130 **/
|
||||
|
||||
lcd_write_reg(R_FRAME_CYCLE_CONTROL, 0x0002); /* EQ=0, 18 clks/line */
|
||||
lcd_write_reg(R_DISP_CONTROL1, 0x0036); /* GON=1, DTE=1, REV=1, D1-0=10 */
|
||||
sleep(2);
|
||||
|
||||
lcd_write_reg(R_DISP_CONTROL1, 0x0026); /* GON=1, DTE=0, REV=1, D1-0=10 */
|
||||
sleep(2);
|
||||
|
||||
lcd_write_reg(R_DISP_CONTROL1, 0x0000); /* GON=0, DTE=0, D1-0=00 */
|
||||
|
||||
lcd_write_reg(R_POWER_CONTROL1, 0x0000); /* SAP2-0=000, AP2-0=000 */
|
||||
lcd_write_reg(R_POWER_CONTROL3, 0x0000); /* PON=0 */
|
||||
lcd_write_reg(R_POWER_CONTROL4, 0x0000); /* VCOMG=0 */
|
||||
|
||||
/* datasheet p. 131 */
|
||||
lcd_write_reg(R_POWER_CONTROL1, 0x0001); /* STB=1: standby mode */
|
||||
|
||||
display_on=false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*** update functions ***/
|
||||
|
||||
/* Performance function that works with an external buffer
|
||||
note that by and bheight are in 8-pixel units! */
|
||||
void lcd_blit(const fb_data* data, int x, int by, int width,
|
||||
int bheight, int stride)
|
||||
{
|
||||
/* TODO: Implement lcd_blit() */
|
||||
(void)data;
|
||||
(void)x;
|
||||
(void)by;
|
||||
(void)width;
|
||||
(void)bheight;
|
||||
(void)stride;
|
||||
/*if(display_on)*/
|
||||
}
|
||||
|
||||
/* Line write helper function for lcd_yuv_blit. Write two lines of yuv420.
|
||||
* y should have two lines of Y back to back.
|
||||
* bu and rv should contain the Cb and Cr data for the two lines of Y.
|
||||
* Needs EMAC set to saturated, signed integer mode.
|
||||
*/
|
||||
extern void lcd_write_yuv420_lines(const unsigned char *y,
|
||||
const unsigned char *bu,
|
||||
const unsigned char *rv, int width);
|
||||
|
||||
/* Performance function to blit a YUV bitmap directly to the LCD
|
||||
* src_x, src_y, width and height should be even
|
||||
* x, y, width and height have to be within LCD bounds
|
||||
*/
|
||||
void lcd_yuv_blit(unsigned char * const src[3],
|
||||
int src_x, int src_y, int stride,
|
||||
int x, int y, int width, int height)
|
||||
{
|
||||
/* IRAM Y, Cb and Cb buffers. */
|
||||
unsigned char y_ibuf[LCD_WIDTH*2];
|
||||
unsigned char bu_ibuf[LCD_WIDTH/2];
|
||||
unsigned char rv_ibuf[LCD_WIDTH/2];
|
||||
const unsigned char *ysrc, *usrc, *vsrc;
|
||||
const unsigned char *ysrc_max;
|
||||
|
||||
if (!display_on)
|
||||
return;
|
||||
|
||||
width &= ~1; /* stay on the safe side */
|
||||
height &= ~1;
|
||||
|
||||
/* Set start position and window */
|
||||
lcd_write_reg(R_VERT_RAM_ADDR_POS,((x+xoffset+width-1) << 8) | (x+xoffset));
|
||||
lcd_write_reg(R_RAM_ADDR_SET, ((x+xoffset) << 8) | y);
|
||||
|
||||
lcd_begin_write_gram();
|
||||
|
||||
ysrc = src[0] + src_y * stride + src_x;
|
||||
usrc = src[1] + (src_y * stride >> 2) + (src_x >> 1);
|
||||
vsrc = src[2] + (src_y * stride >> 2) + (src_x >> 1);
|
||||
ysrc_max = ysrc + height * stride;
|
||||
|
||||
coldfire_set_macsr(EMAC_SATURATE);
|
||||
do
|
||||
{
|
||||
memcpy(y_ibuf, ysrc, width);
|
||||
memcpy(y_ibuf + width, ysrc + stride, width);
|
||||
memcpy(bu_ibuf, usrc, width >> 1);
|
||||
memcpy(rv_ibuf, vsrc, width >> 1);
|
||||
lcd_write_yuv420_lines(y_ibuf, bu_ibuf, rv_ibuf, width);
|
||||
ysrc += 2 * stride;
|
||||
usrc += stride >> 1;
|
||||
vsrc += stride >> 1;
|
||||
}
|
||||
while (ysrc < ysrc_max);
|
||||
}
|
||||
|
||||
/* Update the display.
|
||||
This must be called after all other LCD functions that change the display. */
|
||||
void lcd_update(void) ICODE_ATTR;
|
||||
void lcd_update(void)
|
||||
{
|
||||
if(display_on){
|
||||
/* reset update window */
|
||||
lcd_write_reg(R_VERT_RAM_ADDR_POS,((xoffset+219)<<8) | xoffset);
|
||||
|
||||
/* Copy display bitmap to hardware */
|
||||
lcd_write_reg(R_RAM_ADDR_SET, xoffset << 8);
|
||||
lcd_begin_write_gram();
|
||||
|
||||
DAR3 = 0xf0000002;
|
||||
SAR3 = (unsigned long)lcd_framebuffer;
|
||||
BCR3 = LCD_WIDTH*LCD_HEIGHT*2;
|
||||
DCR3 = DMA_AA | DMA_BWC(1)
|
||||
| DMA_SINC | DMA_SSIZE(DMA_SIZE_LINE)
|
||||
| DMA_DSIZE(DMA_SIZE_WORD) | DMA_START;
|
||||
|
||||
while (!(DSR3 & 1));
|
||||
DSR3 = 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Update a fraction of the display. */
|
||||
void lcd_update_rect(int, int, int, int) ICODE_ATTR;
|
||||
void lcd_update_rect(int x, int y, int width, int height)
|
||||
{
|
||||
unsigned long dma_addr;
|
||||
|
||||
if(display_on) {
|
||||
|
||||
if(x + width > LCD_WIDTH)
|
||||
width = LCD_WIDTH - x;
|
||||
if(width <= 0) /* nothing to do */
|
||||
return;
|
||||
if(y + height > LCD_HEIGHT)
|
||||
height = LCD_HEIGHT - y;
|
||||
|
||||
/* set update window */
|
||||
|
||||
lcd_write_reg(R_VERT_RAM_ADDR_POS,((x+xoffset+width-1) << 8) | (x+xoffset));
|
||||
lcd_write_reg(R_RAM_ADDR_SET, ((x+xoffset) << 8) | y);
|
||||
lcd_begin_write_gram();
|
||||
|
||||
DAR3 = 0xf0000002;
|
||||
dma_addr = (unsigned long)&lcd_framebuffer[y][x];
|
||||
width *= 2;
|
||||
|
||||
for (; height > 0; height--)
|
||||
{
|
||||
SAR3 = dma_addr;
|
||||
BCR3 = width;
|
||||
DCR3 = DMA_AA | DMA_BWC(1)
|
||||
| DMA_SINC | DMA_SSIZE(DMA_SIZE_LINE)
|
||||
| DMA_DSIZE(DMA_SIZE_WORD) | DMA_START;
|
||||
|
||||
dma_addr += LCD_WIDTH*2;
|
||||
|
||||
while (!(DSR3 & 1));
|
||||
DSR3 = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -147,6 +147,10 @@ static inline void invalidate_icache(void)
|
|||
#endif
|
||||
void coldfire_set_pllcr_audio_bits(long bits);
|
||||
|
||||
#ifdef HRIVER_H100_SERIES
|
||||
bool detect_flashed_rockbox(void);
|
||||
#endif
|
||||
|
||||
/* 11.2896 MHz */
|
||||
#define CPUFREQ_DEFAULT_MULT 1
|
||||
#define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue