firmware: add RegGen description for STM32H743

Change-Id: I084c54bd1c2c2974e5fd0b1bfea68697b2b394ba
2026-04-11 16:37:45 -04:00 · 2025-12-21 20:02:12 +00:00 · 2025-12-21 20:02:12 +00:00 · e7b139b06a
commit e7b139b06a
parent a3d16e34ec
1 changed files with 708 additions and 0 deletions
--- a/firmware/reggen/stm32h743.regs
+++ b/firmware/reggen/stm32h743.regs
@ -0,0 +1,708 @@
+// This file is marked CC0 1.0.
+// To view a copy of this mark, visit https://creativecommons.org/publicdomain/zero/1.0/
+
+// Register definitions for STM32H743
+
+FLASH @ 0x52002000 : block {
+    ACR @ 0x00 : reg {
+        5 4 WRHIGHFREQ
+        3 0 LATENCY
+    }
+}
+
+PWR @ 0x58024800 : block {
+    CR1 @ 0x00 : reg {
+        18 17 ALS
+        -- 16 AVDEN
+        15 14 SVOS
+        -- 09 FLPS
+        -- 08 DBP
+        07 05 PLS
+        -- 04 PVDE
+        -- 00 LPDS
+    }
+
+    CSR1 @ 0x04 : reg {
+        -- 16 AVDO
+        15 14 ACTVOS
+        -- 13 ACTVOSRDY
+        -- 04 PVDO
+    }
+
+    CR3 @ 0x0c : reg {
+        26 USB33RDY
+        25 USBREGEN
+        24 USB33DEN
+        09 VBRS
+        08 VBE
+        02 SCUEN
+        01 LDOEN
+        00 BYPASS
+    }
+
+    D3CR @ 0x18 : reg {
+        15 14 VOS    : { 1 = VOS3; 2 = VOS2; 3 = VOS1; }
+        -- 13 VOSRDY
+    }
+}
+
+RCC @ 0x58024400 : block {
+    CR @ 0x00 : reg {
+        -- 29 PLL3RDY
+        -- 28 PLL3ON
+        -- 27 PLL2RDY
+        -- 26 PLL2ON
+        -- 25 PLL1RDY
+        -- 24 PLL1ON
+        -- 19 HSECSSON
+        -- 18 HSEBYP
+        -- 17 HSERDY
+        -- 16 HSEON
+        -- 15 D2CKRDY
+        -- 14 D1CKRDY
+        -- 13 HSI48RDY
+        -- 12 HSI48ON
+        -- 09 CSIKERON
+        -- 08 CSIRDY
+        -- 07 CSION
+        -- 05 HSIDIVF
+        04 03 HSIDIV
+        -- 02 HSIRDY
+        -- 01 HSIKERON
+        -- 00 HSION
+    }
+
+    CFGR @ 0x10 : reg {
+        enum SWCLK {
+            0 = HSI
+            1 = CSI
+            2 = HSE
+            3 = PLL1P
+        }
+
+        31 29 MCO2    : { 0 = SYSCLK; 1 = PLL2P; 2 = HSE; 3 = PLL1P; 4 = CSI; 5 = LSI }
+        28 25 MCO2PRE
+        24 22 MCO1    : { 0 = HSI; 1 = LSE; 2 = HSE; 3 = PLL1Q; 4 = HSI48 }
+        21 18 MCO1PRE
+        -- 15 TIMPRE
+        -- 14 HRTIMSEL
+        13 08 RTCPRE
+        -- 07 STOPKERWUCK
+        -- 06 STOPWUCK
+        05 03 SWS : SWCLK
+        02 00 SW  : SWCLK
+    }
+
+    D1CFGR @ 0x18 : reg {
+        11 08 D1CPRE
+        06 04 D1PPRE
+        03 00 HPRE
+    }
+
+    D2CFGR @ 0x1c : reg {
+        10 08 D2PPRE2
+        06 04 D2PPRE1
+    }
+
+    D3CFGR @ 0x20 : reg {
+        06 04 D3PPRE
+    }
+
+    PLLCKSELR @ 0x28 : reg {
+        25 20 DIVM3
+        17 12 DIVM2
+        09 04 DIVM1
+        01 00 PLLSRC : { 0 = HSI; 1 = CSI; 2 = HSE; 3 = NONE }
+    }
+
+    PLLCFGR @ 0x2c : reg {
+        enum PLLRGE {
+            0 = 1_2MHZ;
+            1 = 2_4MHZ;
+            2 = 4_8MHZ;
+            3 = 8_16MHZ;
+        }
+
+        enum PLLVCOSEL {
+            0 = WIDE
+            1 = MEDIUM
+        }
+
+        -- 24 DIVR3EN
+        -- 23 DIVQ3EN
+        -- 22 DIVP3EN
+        -- 21 DIVR2EN
+        -- 20 DIVQ2EN
+        -- 19 DIVP2EN
+        -- 18 DIVR1EN
+        -- 17 DIVQ1EN
+        -- 16 DIVP1EN
+        11 10 PLL3RGE    : PLLRGE
+        -- 09 PLL3VCOSEL : PLLVCOSEL
+        -- 08 PLL3FRACEN
+        07 06 PLL2RGE    : PLLRGE
+        -- 05 PLL2VCOSEL : PLLVCOSEL
+        -- 04 PLL2FRACEN
+        03 02 PLL1RGE    : PLLRGE
+        -- 01 PLL1VCOSEL : PLLVCOSEL
+        -- 00 PLL1FRACEN
+    }
+
+    reg PLLxDIVR {
+        30 24 DIVR
+        22 16 DIVQ
+        15 09 DIVP
+        08 00 DIVN
+    }
+
+    reg PLLxFRACR {
+        15 03 FRACN
+    }
+
+    PLL1DIVR  @ 0x30 : PLLxDIVR
+    PLL1FRACR @ 0x34 : PLLxFRACR
+    PLL2DIVR  @ 0x38 : PLLxDIVR
+    PLL2FRACR @ 0x3c : PLLxFRACR
+    PLL3DIVR  @ 0x40 : PLLxDIVR
+    PLL3FRACR @ 0x44 : PLLxFRACR
+
+    D1CCIPR @ 0x4c : reg {
+        enum QSPI_FMC_SEL {
+            0 = AHB
+            1 = PLL1Q
+            2 = PLL2R
+            3 = PER
+        }
+
+        29 28 CKPERSEL : { 0 = HSI;   1 = CSI;  2 = HSE }
+        -- 16 SDMMCSEL : { 0 = PLL1Q; 2 = PLL2R }
+        05 04 QSPISEL  : QSPI_FMC_SEL
+        01 00 FMCSEL   : QSPI_FMC_SEL
+    }
+
+    enum AUDIO_CLK_SEL {
+        0 = PLL1Q
+        1 = PLL2P
+        2 = PLL3P
+        3 = I2SCKIN
+        4 = PER
+    }
+
+    D2CCIP1R @ 0x50 : reg {
+        -- 31 SWPSEL    : { 0 = APB1;  1 = HSI }
+        29 28 FDCANSEL  : { 0 = HSE;   1 = PLL1Q; 2 = PLL2Q }
+        -- 24 DFSDM1SEL : { 0 = APB2;  1 = SYSCLK }
+        21 20 SPDIFSEL  : { 0 = PLL1Q; 1 = PLL2R; 2 = PLL3R; 3 = HSI }
+        18 16 SPI45SEL  : { 0 = APB2;  1 = PLL2Q; 2 = PLL3Q; 3 = HSI; 4 = CSI; 5 = HSE }
+        14 12 SPI123SEL : AUDIO_CLK_SEL
+        08 06 SAI23SEL  : AUDIO_CLK_SEL
+        02 00 SAI1SEL   : AUDIO_CLK_SEL
+    }
+
+    D2CCIP2R @ 0x54 : reg {
+        enum USARTSEL_COMMON {
+            1 = PLL2Q
+            2 = PLL3Q
+            3 = HSI
+            4 = CSI
+            5 = LSE
+        }
+
+        30 28 LPTIM1SEL      : { 0 = APB1; 1 = PLL2P; 2 = PLL3R; 3 = LSE;  4 = LSI; 5 = PER }
+        23 22 CECSEL         : { 0 = LSE;  1 = LSI;   2 = CSI }
+        21 20 USBSEL         : { 0 = OFF;  1 = PLL1Q; 2 = PLL3Q; 3 = HSI48 }
+        13 12 I2C123SEL      : { 0 = APB1; 1 = PLL3R; 2 = HSI;   3 = CSI }
+        09 08 RNGSEL         : { 0 = HSI;  1 = PLL1Q; 2 = LSE;   3 = LSI }
+        05 03 USART16SEL     : { 0 = APB2; include USARTSEL_COMMON }
+        02 00 USART234578SEL : { 0 = APB1; include USARTSEL_COMMON }
+    }
+
+    D3CCIPR @ 0x58 : reg {
+        enum LPTIMSEL {
+            0 = APB4
+            1 = PLL2P
+            2 = PLL3R
+            3 = LSE
+            4 = LSI
+            5 = PER
+        }
+
+        30 28 SPI6SEL     : { 0 = APB4;  1 = PLL2Q; 2 = PLL3Q; 3 = HSI; 4 = CSI; 5 = HSE }
+        26 24 SAI4BSEL    : AUDIO_CLK_SEL
+        23 21 SAI4ASEL    : AUDIO_CLK_SEL
+        17 16 ADCSEL      : { 0 = PLL2P; 1 = PLL3R; 2 = PER }
+        15 13 LPTIM345SEL : LPTIMSEL
+        12 10 LPTIM2SEL   : LPTIMSEL
+        09 08 I2C4SEL     : { 0 = APB4; 1 = PLL3R; 2 = HSI;   3 = CSI }
+        02 00 LPUART1SEL  : { 0 = APB4; 1 = PLL2Q; 2 = PLL3Q; 3 = HSI; 4 = CSI; 5 = LSE }
+    }
+
+    BDCR @ 0x70 : reg {
+        -- 16 BDRST
+        -- 15 RTCEN
+        09 08 RTCSEL : { 0 = NONE; 1 = LSE; 2 = LSI; 3 = HSE }
+        -- 06 LSECSSD
+        -- 05 LSECSSON
+        04 03 LSEDRV : { 0 = LOW; 1 = MED_LOW; 2 = MED_HIGH; 3 = HIGH }
+        -- 02 LSEBYP
+        -- 01 LSERDY
+        -- 00 LSEON
+    }
+
+    CSR @ 0x74 : reg {
+        1 LSIRDY
+        0 LSION
+    }
+
+    AHB3ENR @ 0xd4 : reg {
+        16 SDMMC1EN
+        14 QSPIEN
+        12 FMCEN
+        05 JPEGDECEN
+        04 DMA2DEN
+        00 MDMAEN
+    }
+
+    AHB3LPENR @ 0xfc : reg {
+        include AHB3ENR
+
+        31 AXISRAMEN
+        30 ITCMEN
+        29 DTCM2EN
+        28 D1DTCM1EN
+        08 FLASHEN
+    }
+
+    reg AHB4EN_COMMON {
+        28 BKPRAMEN
+        24 ADC3EN
+        21 BDMAEN
+        19 CRCEN
+        10 GPIOKEN
+        09 GPIOJEN
+        08 GPIOIEN
+        07 GPIOHEN
+        06 GPIOGEN
+        05 GPIOFEN
+        04 GPIOEEN
+        03 GPIODEN
+        02 GPIOCEN
+        01 GPIOBEN
+        00 GPIOAEN
+    }
+
+    AHB4ENR @ 0xe0 : reg {
+        include AHB4EN_COMMON
+
+        25 HSEMEN
+    }
+
+    AHB4LPENR @ 0x108 : reg {
+        include AHB4EN_COMMON
+
+        29 SRAM4EN
+    }
+
+    reg APB3ENR {
+        6 WWDG1EN
+        3 LTDCEN
+    }
+
+    APB3LPENR @ 0x10c : APB3ENR
+    APB3ENR @ 0xe4 : APB3ENR
+
+    reg APB1LENR {
+        31 UART8EN
+        30 UART7EN
+        29 DAC12EN
+        27 CECEN
+        23 I2C3EN
+        22 I2C2EN
+        21 I2C1EN
+        20 UART5EN
+        19 UART4EN
+        18 USART3EN
+        17 USART2EN
+        16 SPDIFRXEN
+        15 SPI3EN
+        14 SPI2EN
+        09 LPTIM1EN
+        08 TIM14EN
+        07 TIM13EN
+        06 TIM12EN
+        05 TIM7EN
+        04 TIM6EN
+        03 TIM5EN
+        02 TIM4EN
+        01 TIM3EN
+        00 TIM2EN
+    }
+
+    APB1LENR @ 0xe8 : APB1LENR
+    APB1LLPENR @ 0x110 : APB1LENR
+
+    reg APB1HENR {
+        8 FDCANEN
+        5 MDIOSEN
+        4 OPAMPEN
+        2 SWPEN
+        1 CRSEN
+    }
+
+    APB1HENR @ 0xec : APB1HENR
+    APB1HLPENR @ 0x114 : APB1HENR
+
+    reg APB2ENR {
+        29 HRTIMEN
+        28 DFSDM1EN
+        24 SAI3EN
+        23 SAI2EN
+        22 SAI1EN
+        20 SPI5EN
+        18 TIM17EN
+        17 TIM16EN
+        16 TIM15EN
+        13 SPI4EN
+        12 SPI1EN
+        05 USART6EN
+        04 USART1EN
+        01 TIM8EN
+        00 TIM1EN
+    }
+
+    APB2ENR @ 0xf0 : APB2ENR
+    APB2LPENR @ 0x118 : APB2ENR
+
+    reg APB4ENR {
+        21 SAI4EN
+        16 RTCAPBEN
+        15 VREFEN
+        14 COMP12EN
+        12 LPTIM5EN
+        11 LPTIM4EN
+        10 LPTIM3EN
+        09 LPTIM2EN
+        07 I2C4EN
+        05 SPI6EN
+        03 LPUART1EN
+        01 SYSCFGEN
+    }
+
+    APB4ENR @ 0xf4 : APB4ENR
+    APB4LPENR @ 0x11c : APB4ENR
+}
+
+GPIO @ 0x58020000 [11; 0x400] : block {
+    MODER   @ 0x00 : reg
+    OTYPER  @ 0x04 : reg
+    OSPEEDR @ 0x08 : reg
+    PUPDR   @ 0x0c : reg
+    IDR     @ 0x10 : reg
+    ODR     @ 0x14 : reg
+    BSRR    @ 0x18 : reg
+    LCKR    @ 0x1c : reg
+    AFRL    @ 0x20 : reg
+    AFRH    @ 0x24 : reg
+}
+
+SYSCFG @ 0x58000400 : block {
+    PWRCFG @ 0x2c : reg {
+        0 ODEN
+    }
+}
+
+FMC @ 0x52004000 : block {
+    BCR @ 0x00 [4; 0x08]: reg {
+        -- 31 FMCEN
+        25 24 BMAP
+        -- 21 WFDIS
+        -- 20 CCLKEN
+        -- 19 CBURSTRW
+        18 16 CPSIZE : { 0 = NONE; 1 = 128BYTE; 2 = 256BYTE; 4 = 1024BYTE }
+        -- 15 ASYNCWAIT
+        -- 14 EXTMOD
+        -- 13 WAITEN
+        -- 12 WREN
+        -- 11 WAITCFG
+        -- 09 WAITPOL
+        -- 08 BURSTEN
+        -- 06 FACCEN
+        05 04 MWID : { 0 = 8BIT; 1 = 16BIT; 2 = 32BIT }
+        03 02 MTYP : { 0 = SRAM; 1 = PSRAM; 2 = NOR }
+        -- 01 MUXEN
+        -- 00 MBKEN
+    }
+
+    BTR @ 0x04 [4; 0x08] : reg {
+        29 28 ACCMOD
+        27 24 DLAT
+        23 20 CLKDIV
+        19 16 BUSTURN
+        15 08 DATAST
+        07 04 ADDHLD
+        03 00 ADDSET
+    }
+
+    SDCR @ 0x140 [2; 0x04] : reg {
+        14 13 RPIPE
+        -- 12 RBURST
+        11 10 SDCLK
+        -- 09 WP
+        08 07 CAS
+        -- 06 NB
+        05 04 MWID
+        03 02 NR
+        01 00 NC
+    }
+
+    SDTR @ 0x148 [2; 0x04] : reg {
+        27 24 TRCD
+        23 20 TRP
+        19 16 TWR
+        15 12 TRC
+        11 08 TRAS
+        07 04 TXSR
+        03 00 TMRD
+    }
+
+    SDCMR @ 0x150 : reg {
+        22 09 MRD
+        08 05 NRFS
+        -- 04 CTB1
+        -- 03 CTB2
+        02 00 MODE
+    }
+
+    SDRTR @ 0x154 : reg {
+        -- 14 REIE
+        13 01 COUNT
+        -- 00 CRE
+    }
+
+    SDSR @ 0x158 : reg {
+        04 03 MODES2
+        02 01 MODES1
+        -- 00 RE
+    }
+}
+
+RTC @ 0x58004000 : block {
+    reg TR {
+        -- 22 PM
+        21 20 HT
+        19 16 HU
+        14 12 MNT
+        11 08 MNU
+        06 04 ST
+        03 00 SU
+    }
+
+    TR @ 0x00 : TR
+    TSTR @ 0x30 : TR
+
+    reg DR {
+        23 20 YT
+        19 16 YU
+        15 13 WDU
+        -- 12 MT
+        11 08 MU
+        05 04 DT
+        03 00 DU
+    }
+
+    DR @ 0x04 : DR
+    DRTR @ 0x34 : DR
+
+    CR @ 0x08 : reg {
+        -- 24 ITSE
+        -- 23 COE
+        22 21 OSEL : { 0 = DISABLED; 1 = ALARM_A; 2 = ALARM_B; 3 = WAKEUP }
+        -- 20 POL
+        -- 19 COSEL
+        -- 18 BKP
+        -- 17 SUB1H
+        -- 16 ADD1H
+        -- 15 TSIE
+        -- 14 WUTIE
+        -- 13 ALRBIE
+        -- 12 ALRAIE
+        -- 11 TSE
+        -- 10 WUTE
+        -- 09 ALRBE
+        -- 08 ALRAE
+        -- 06 FMT
+        -- 05 BYPSHAD
+        -- 04 REFCKON
+        -- 03 TSEDGE
+        02 00 WUCKSEL : { 0 = RTC_16; 1 = RTC_8; 2 = RTC_4; 3 = RTC_2; 4 = CK_SPRE; 6 = CK_SPRE_ADDWUT }
+    }
+
+    ISR @ 0x0c : reg {
+        17 ITSF
+        16 RECANPF
+        15 TAMP3F
+        14 TAMP2F
+        13 TAMP1F
+        12 TSOVF
+        11 TSF
+        10 WUTF
+        09 ALRBF
+        08 ALRAF
+        07 INIT
+        06 INITF
+        05 RSF
+        04 INITS
+        03 SHPF
+        02 WUTWF
+        01 ALRBWF
+        00 ALRAWF
+    }
+
+    PRER @ 0x10 : reg {
+        22 16 PREDIV_A
+        14 00 PREDIV_S
+    }
+
+    WPR @ 0x24 : reg {
+        07 00 KEY : { 0xCA = KEY1; 0x53 = KEY2 }
+    }
+
+    reg SSR {
+        15 00 SS
+    }
+
+    SSR @ 0x28 : SSR
+    TSSSR @ 0x38 : SSR
+
+    OR @ 0x4c : reg {
+        1 OUT_RMP
+        0 ALARM_TYPE : { 0 = OPEN_DRAIN; 1 = PUSH_PULL }
+    }
+
+    BKPR @ 0x50 [32; 0x04] : reg
+}
+
+block SPI {
+    CR1 @ 0x00 : reg {
+        16 IO_LOCK
+        15 TCRCINI
+        14 RCRCINI
+        13 CRC33_17
+        12 SSI
+        11 HDDIR
+        10 CSUSP
+        09 CSTART
+        08 MASRX
+        00 SPE
+    }
+
+    CR2 @ 0x04 : reg {
+        31 16 TSER
+        15 00 TSIZE
+    }
+
+    CFG1 @ 0x08 : reg {
+        30 28 MBR
+        -- 22 CRCEN
+        20 16 CRCSIZE
+        -- 15 TXDMAEN
+        -- 14 RXDMAEN
+        12 11 UDRDET
+        10 09 UDRCFG
+        08 05 FTHLV
+        04 00 DSIZE
+    }
+
+    CFG2 @ 0x0c : reg {
+        -- 31 AFCNTR
+        -- 30 SSOM
+        -- 29 SSOE
+        -- 28 SSIOP
+        -- 26 SSM : { 0 = SS_PAD; 1 = SSI_BIT }
+        -- 25 CPOL
+        -- 24 CPHA
+        -- 23 LSBFIRST
+        -- 22 MASTER
+        21 19 SP   : { 0 = MOTOROLA; 1 = TI }
+        18 17 COMM : { 0 = DUPLEX; 1 = TXONLY; 2 = RXONLY; 3 = HALF_DUPLEX }
+        -- 15 IOSWP
+        07 04 MIDI
+        03 00 MSSI
+    }
+
+    IER @ 0x10 : reg {
+        10 TSERFIE
+        09 MODFIE
+        08 TIFREIE
+        07 CRCEIE
+        06 OVRIE
+        05 UDRIE
+        04 TXTFIE
+        03 EOTIE
+        02 DXPIE
+        01 TXPIE
+        00 RXPIE
+    }
+
+    SR @ 0x14 : reg {
+       31 16 CTSIZE
+       -- 15 RXWNE
+       14 13 RXPLVL
+       -- 12 TXC
+       -- 11 SUSP
+       -- 10 TSERF
+       -- 09 MODF
+       -- 08 TIFRE
+       -- 07 CRCE
+       -- 06 OVR
+       -- 05 UDR
+       -- 04 TXTF
+       -- 03 EOT
+       -- 02 DXP
+       -- 01 TXP
+       -- 00 RXP
+    }
+
+    IFCR @ 0x18 : reg {
+        11 SUSPC
+        10 TSERFC
+        09 MODFC
+        08 TIFREC
+        07 CRCEC
+        06 OVRC
+        05 UDRC
+        04 TXTFC
+        03 EOTC
+    }
+
+    DR @ 0x20 : reg32
+    CRCPOLY @ 0x40 : reg
+    TXCRC @ 0x44 : reg
+    RXCRC @ 0x48 : reg
+    UDRDR @ 0x4c : reg
+
+    I2SCFGR @ 0x50 : reg {
+        -- 25 MCKOE
+        -- 24 ODD
+        23 16 I2SDIV
+        -- 14 DATFMT : { 0 = RIGHT_ALIGNED; 1 = LEFT_ALIGNED }
+        -- 13 WSINV
+        -- 12 FIXCH
+        -- 11 CKPOL
+        -- 10 CHLEN   : { 0 = 16BIT; 1 = 32BIT }
+        09 08 DATLEN  : { 0 = 16BIT; 1 = 24BIT; 2 = 32BIT }
+        -- 07 PCMSYNC : { 0 = SHORT; 1 = LONG }
+        05 04 I2SSTD  : { 0 = I2S; 1 = MSB_JUSTIFIED; 2 = LSB_JUSTIFIED; 3 = PCM }
+        03 01 I2SCFG  : { 0 = SLAVE_TX; 1 = SLAVE_RX;
+                          2 = MASTER_TX; 3 = MASTER_RX;
+                          4 = SLAVE_DUPLEX; 5 = MASTER_DUPLEX }
+        -- 00 I2SMOD
+    }
+}
+
+SPI1 @ 0x40013000 : SPI
+SPI2 @ 0x40003800 : SPI
+SPI3 @ 0x40003c00 : SPI
+SPI4 @ 0x40013400 : SPI
+SPI5 @ 0x40015000 : SPI
+SPI6 @ 0x58001400 : SPI