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TCC: Implement ECC error correction for sectors read from NAND. Tested on D2 (78x, MLC) and M200 (77x, SLC).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22284 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rob Purchase
parent
4c5ae4b068
commit
e783d0c82a
3 changed files with 169 additions and 75 deletions
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@ -182,51 +182,43 @@
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/* ECC controller */
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#define ECC_CTRL (*(volatile unsigned long *)0x80000900)
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#define ECC_DMA_REQ (1<<28)
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#define ECC_ENC (1<<27) /* MLC ECC3/4 */
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#define ECC_FLG (1<<26)
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#define ECC_IEN (1<<25)
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#define ECC_MANUAL (1<<22)
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#define ECC_WCNT (1<<12) /* [21:12] */
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#define ECC_HOLD (1<<7)
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#define ECC_M4EN (1<<6)
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#define ECC_ZERO (1<<5)
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#define ECC_M3EN (1<<4)
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#define ECC_CNT_MASK (7<<1)
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#define ECC_CNT (1<<1)
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#define ECC_SLC (1<<0)
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#define ECC_CTRL (*(volatile unsigned long *)0x80000900)
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#define ECC_DMA_REQ (1<<28)
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#define ECC_ENC (1<<27) /* MLC ECC3/4 */
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#define ECC_READY (1<<26)
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#define ECC_IEN (1<<25)
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#define ECC_MANUAL (1<<22)
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#define ECC_WCNT (1<<12) /* [21:12] */
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#define ECC_HOLD (1<<7)
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#define ECC_M4EN (1<<6)
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#define ECC_ZERO (1<<5)
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#define ECC_M3EN (1<<4)
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#define ECC_CNT_MASK (7<<1)
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#define ECC_CNT (1<<1)
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#define ECC_SLC (1<<0)
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#define ECC_BASE (*(volatile unsigned long *)0x80000904)
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#define ECC_MASK (*(volatile unsigned long *)0x80000908)
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#define ECC_CLR (*(volatile unsigned long *)0x8000090c)
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#define SLC_ECC0 (*(volatile unsigned long *)0x80000910)
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#define SLC_ECC1 (*(volatile unsigned long *)0x80000914)
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#define SLC_ECC2 (*(volatile unsigned long *)0x80000918)
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#define SLC_ECC3 (*(volatile unsigned long *)0x8000091c)
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#define SLC_ECC4 (*(volatile unsigned long *)0x80000920)
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#define SLC_ECC5 (*(volatile unsigned long *)0x80000924)
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#define SLC_ECC6 (*(volatile unsigned long *)0x80000928)
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#define SLC_ECC7 (*(volatile unsigned long *)0x8000092c)
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#define MLC_ECC0W (*(volatile unsigned long *)0x80000930)
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#define MLC_ECC1W (*(volatile unsigned long *)0x80000934)
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#define MLC_ECC2W (*(volatile unsigned long *)0x80000938)
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#define MLC_ECC0R (*(volatile unsigned long *)0x80000940)
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#define MLC_ECC1R (*(volatile unsigned long *)0x80000944)
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#define MLC_ECC2R (*(volatile unsigned long *)0x80000948)
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#define ECC_BASE (*(volatile unsigned long *)0x80000904)
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#define ECC_MASK (*(volatile unsigned long *)0x80000908)
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#define ECC_CLR (*(volatile unsigned long *)0x8000090c)
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#define SLC_ECC0 (*(volatile unsigned long *)0x80000910)
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#define SLC_ECC1 (*(volatile unsigned long *)0x80000914)
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#define SLC_ECC2 (*(volatile unsigned long *)0x80000918)
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#define SLC_ECC3 (*(volatile unsigned long *)0x8000091c)
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#define SLC_ECC4 (*(volatile unsigned long *)0x80000920)
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#define SLC_ECC5 (*(volatile unsigned long *)0x80000924)
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#define SLC_ECC6 (*(volatile unsigned long *)0x80000928)
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#define SLC_ECC7 (*(volatile unsigned long *)0x8000092c)
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#define MLC_ECC0W (*(volatile unsigned long *)0x80000930)
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#define MLC_ECC1W (*(volatile unsigned long *)0x80000934)
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#define MLC_ECC2W (*(volatile unsigned long *)0x80000938)
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#define MLC_ECC0R (*(volatile unsigned long *)0x80000940)
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#define MLC_ECC1R (*(volatile unsigned long *)0x80000944)
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#define MLC_ECC2R (*(volatile unsigned long *)0x80000948)
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#define ECC_CORR_START (*(volatile unsigned long *)0x8000094c)
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#define ECC_ERRADDR1 (*(volatile unsigned long *)0x80000950)
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#define ECC_ERRADDR2 (*(volatile unsigned long *)0x80000954)
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#define ECC_ERRADDR3 (*(volatile unsigned long *)0x80000958)
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#define ECC_ERRADDR4 (*(volatile unsigned long *)0x8000095c)
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#define ECC_ERRDATA1 (*(volatile unsigned long *)0x80000960)
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#define ECC_ERRDATA2 (*(volatile unsigned long *)0x80000964)
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#define ECC_ERRDATA3 (*(volatile unsigned long *)0x80000968)
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#define ECC_ERRDATA4 (*(volatile unsigned long *)0x8000096c)
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#define ECC_ERR_NUM (*(volatile unsigned long *)0x80000970)
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#define ECC_ERRADDR(x) (*(volatile unsigned long *)(0x80000950+4*(x)))
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#define ECC_ERRDATA(x) (*(volatile unsigned long *)(0x80000960+4*(x)))
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#define ECC_ERR_NUM (*(volatile unsigned long *)0x80000970)
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#define ECC_ERRDATA(x) (*(volatile unsigned long *)(0x80000960 + (x) * 4))
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#define ECC_ERRADDR(x) (*(volatile unsigned long *)(0x80000950 + (x) * 4))
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/* Digital Audio Interface */
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#define DADI_L0 (*(volatile unsigned long *)0x80000000)
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@ -232,18 +232,18 @@
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/* ECC Controller */
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#define ECC_CTRL (*(volatile unsigned long *)0xF005B000)
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#define ECC_M4EN (1<<6)
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#define ECC_ENC (1<<27)
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#define ECC_READY (1<<26)
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#define ECC_BASE (*(volatile unsigned long *)0xF005B004)
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#define ECC_CLR (*(volatile unsigned long *)0xF005B00C)
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#define ECC_MLC0W (*(volatile unsigned long *)0xF005B030)
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#define ECC_MLC1W (*(volatile unsigned long *)0xF005B034)
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#define ECC_MLC2W (*(volatile unsigned long *)0xF005B038)
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#define ECC_ERRADDR (*(volatile unsigned long *)0xF005B050)
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#define ECC_ERRDATA (*(volatile unsigned long *)0xF005B060)
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#define ECC_ERR (*(volatile unsigned long *)0xF005B070)
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#define ECC_CTRL (*(volatile unsigned long *)0xF005B000)
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#define ECC_ENC (1<<27)
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#define ECC_READY (1<<26)
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#define ECC_M4EN (1<<6)
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#define ECC_BASE (*(volatile unsigned long *)0xF005B004)
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#define ECC_CLR (*(volatile unsigned long *)0xF005B00C)
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#define MLC_ECC0W (*(volatile unsigned long *)0xF005B030)
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#define MLC_ECC1W (*(volatile unsigned long *)0xF005B034)
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#define MLC_ECC2W (*(volatile unsigned long *)0xF005B038)
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#define ECC_ERRADDR(x) (*(volatile unsigned long *)(0xF005B050+4*(x)))
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#define ECC_ERRDATA(x) (*(volatile unsigned long *)(0xF005B060+4*(x)))
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#define ECC_ERR_NUM (*(volatile unsigned long *)0xF005B070)
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/* SD/MMC Controller */
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@ -31,7 +31,10 @@
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#define SECTOR_SIZE 512
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/* #define USE_ECC_CORRECTION */
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/* ECC on read is implemented on the assumption that MLC-style 4-bit correction
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is always used regardless of NAND chip type. This assumption is true for at
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least D2 (MLC) and M200 (SLC). */
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#define USE_ECC_CORRECTION
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/* for compatibility */
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int ata_spinup_time = 0;
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@ -140,12 +143,6 @@ static struct write_cache write_caches[MAX_WRITE_CACHES];
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static int write_caches_in_use = 0;
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#ifdef USE_ECC_CORRECTION
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static unsigned int ecc_sectors_corrected = 0;
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static unsigned int ecc_bits_corrected = 0;
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static unsigned int ecc_fail_count = 0;
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#endif
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/* Conversion functions */
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@ -315,7 +312,7 @@ static void nand_read_uid(int bank, unsigned int* uid_buf)
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}
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static void nand_read_raw(int bank, int row, int column, int size, void* buf)
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static void nand_setup_read(int bank, int row, int column)
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{
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int i;
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@ -355,6 +352,23 @@ static void nand_read_raw(int bank, int row, int column, int size, void* buf)
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/* Wait until complete */
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while (!(NFC_CTRL & NFC_READY)) {};
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}
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static void nand_end_read(void)
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{
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nand_chip_select(-1);
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/* Disable NFC bus clock */
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BCLKCTR &= ~DEV_NAND;
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}
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static void nand_read_raw(int bank, int row, int column, int size, void* buf)
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{
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int i;
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nand_setup_read(bank, row, column);
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/* Read data into page buffer */
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if (((unsigned int)buf & 3) || (size & 3))
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@ -375,10 +389,7 @@ static void nand_read_raw(int bank, int row, int column, int size, void* buf)
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}
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}
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nand_chip_select(-1);
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/* Disable NFC bus clock */
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BCLKCTR &= ~DEV_NAND;
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nand_end_read();
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}
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@ -477,15 +488,106 @@ static void nand_get_chip_info(void)
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static bool nand_read_sector_of_phys_page(int bank, int page,
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int sector, void* buf)
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{
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#ifndef USE_ECC_CORRECTION
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nand_read_raw(bank, page,
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sector * (SECTOR_SIZE+16),
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SECTOR_SIZE, buf);
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return true;
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#else
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/* Not yet implemented */
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return false;
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bool ret = true;
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int i;
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int page_offset = sector * (SECTOR_SIZE + 16);
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#ifdef USE_ECC_CORRECTION
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unsigned long spare_buf[4];
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/* Set up the ECC controller to monitor reads from NFC_WDATA */
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BCLKCTR |= DEV_ECC;
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ECC_BASE = (unsigned long)&NFC_WDATA;
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ECC_CTRL |= ECC_M4EN;
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ECC_CTRL &= ~ECC_ENC;
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ECC_CTRL |= ECC_READY;
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ECC_CLR = 0;
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#endif
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/* Read the sector data */
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nand_setup_read(bank, page, page_offset);
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/* Read data into page buffer */
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if ((unsigned int)buf & 3)
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{
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/* If unaligned, read into a temporary buffer and copy to destination.
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This way, reads are always done through NFC_WDATA - otherwise they
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would not be 'seen' by the ECC controller. */
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static char temp_buf[SECTOR_SIZE];
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unsigned int* ptr = (unsigned int*) temp_buf;
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for (i = 0; i < (SECTOR_SIZE/4); i++)
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{
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*ptr++ = NFC_WDATA;
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}
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memcpy(buf, temp_buf, SECTOR_SIZE);
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}
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else
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{
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/* Use straight word copy as buffer and size are both word-aligned */
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unsigned int* ptr = (unsigned int*) buf;
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for (i = 0; i < (SECTOR_SIZE/4); i++)
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{
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*ptr++ = NFC_WDATA;
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}
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}
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#ifdef USE_ECC_CORRECTION
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/* Stop monitoring before we read the OOB data */
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ECC_CTRL &= ~ECC_M4EN;
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BCLKCTR &= ~DEV_ECC;
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/* Read a further 4 words (sector OOB data) */
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spare_buf[0] = NFC_WDATA;
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spare_buf[1] = NFC_WDATA;
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spare_buf[2] = NFC_WDATA;
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spare_buf[3] = NFC_WDATA;
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/* Calculate MLC4 ECC using bytes 0,1,8-15 */
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BCLKCTR |= DEV_ECC;
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ECC_CTRL |= ECC_M4EN;
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MLC_ECC0W = *(unsigned short*)spare_buf;
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MLC_ECC1W = spare_buf[2];
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MLC_ECC2W = spare_buf[3];
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while (!(ECC_CTRL & ECC_READY)) {};
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int errors = ECC_ERR_NUM & 7;
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switch (errors)
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{
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case 4: /* nothing to correct */
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break;
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case 7: /* fail, can't correct */
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ret = false;
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break;
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default: /* between 1 and 4 errors */
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{
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int i;
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unsigned char* char_buf = (unsigned char*)buf;
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for (i = 0; i < errors + 1; i++)
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{
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int offset = 0x207 - ECC_ERRADDR(i);
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char_buf[offset] ^= ECC_ERRDATA(i);
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}
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}
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}
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/* Disable ECC block */
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ECC_CTRL &= ~ECC_M4EN;
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BCLKCTR &= ~DEV_ECC;
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#endif
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nand_end_read();
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return ret;
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}
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