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Better sound quality on the iAudio X5 using the correct MCLK frequency

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9354 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Linus Nielsen Feltzing 2006-03-30 10:01:04 +00:00
parent 8bdd92b05e
commit e62152ddf9
4 changed files with 10 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

2
firmware/drivers/tlv320.c
View file

@ -81,7 +81,7 @@ void tlv320_init(void)
tlv320_write_reg(REG_DAIF, DAIF_IWL_16|DAIF_FOR_I2S); tlv320_write_reg(REG_DAIF, DAIF_IWL_16|DAIF_FOR_I2S);
tlv320_set_headphone_vol(0, 0); tlv320_set_headphone_vol(0, 0);
tlv320_write_reg(REG_DIA, DIA_ACT); tlv320_write_reg(REG_DIA, DIA_ACT);
tlv320_write_reg(REG_SRC, SRC_CLKIN); tlv320_write_reg(REG_SRC, (8 << 2)); /* 44.1kHz */
} }
/** /**

6
firmware/pcm_playback.c
View file

@ -118,20 +118,20 @@ void pcm_set_frequency(unsigned int frequency)
switch(frequency) switch(frequency)
{ {
case 11025: case 11025:
pcm_freq = 0x4; pcm_freq = 0x2;
#ifdef HAVE_UDA1380 #ifdef HAVE_UDA1380
uda1380_set_nsorder(3); uda1380_set_nsorder(3);
#endif #endif
break; break;
case 22050: case 22050:
pcm_freq = 0x6; pcm_freq = 0x4;
#ifdef HAVE_UDA1380 #ifdef HAVE_UDA1380
uda1380_set_nsorder(3); uda1380_set_nsorder(3);
#endif #endif
break; break;
case 44100: case 44100:
default: default:
pcm_freq = 0xC; pcm_freq = 0x6;
#ifdef HAVE_UDA1380 #ifdef HAVE_UDA1380
uda1380_set_nsorder(5); uda1380_set_nsorder(5);
#endif #endif

6
firmware/system.c
View file

@ -600,7 +600,7 @@ void set_cpu_frequency(long frequency)
/* Refresh timer for bypass frequency */ /* Refresh timer for bypass frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
PLLCR = 0x11856005; PLLCR = 0x11c56005;
CSCR0 = 0x00001180; /* Flash: 4 wait states */ CSCR0 = 0x00001180; /* Flash: 4 wait states */
CSCR1 = 0x00000980; /* LCD: 2 wait states */ CSCR1 = 0x00000980; /* LCD: 2 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@ -617,7 +617,7 @@ void set_cpu_frequency(long frequency)
/* Refresh timer for bypass frequency */ /* Refresh timer for bypass frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
PLLCR = 0x1385e005; PLLCR = 0x13c5e005;
CSCR0 = 0x00000580; /* Flash: 1 wait state */ CSCR0 = 0x00000580; /* Flash: 1 wait state */
CSCR1 = 0x00000180; /* LCD: 0 wait states */ CSCR1 = 0x00000180; /* LCD: 0 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@ -633,7 +633,7 @@ void set_cpu_frequency(long frequency)
/* Refresh timer for bypass frequency */ /* Refresh timer for bypass frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
PLLCR = 0x10800200; /* Power down PLL, but keep CLSEL and CRSEL */ PLLCR = 0x10c00200; /* Power down PLL, but keep CLSEL and CRSEL */
CSCR0 = 0x00000180; /* Flash: 0 wait states */ CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */ CSCR1 = 0x00000180; /* LCD: 0 wait states */
DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */

6
firmware/target/coldfire/iaudio/x5/system-x5.c
View file

@ -37,7 +37,7 @@ void set_cpu_frequency(long frequency)
/* Refresh timer for bypass frequency */ /* Refresh timer for bypass frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
PLLCR = 0x13042045; PLLCR = 0x13442045;
CSCR0 = 0x00001180; /* Flash: 4 wait states */ CSCR0 = 0x00001180; /* Flash: 4 wait states */
CSCR1 = 0x00000980; /* LCD: 2 wait states */ CSCR1 = 0x00000980; /* LCD: 2 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@ -54,7 +54,7 @@ void set_cpu_frequency(long frequency)
/* Refresh timer for bypass frequency */ /* Refresh timer for bypass frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
PLLCR = 0x16030045; PLLCR = 0x16430045;
CSCR0 = 0x00000580; /* Flash: 1 wait state */ CSCR0 = 0x00000580; /* Flash: 1 wait state */
CSCR1 = 0x00000180; /* LCD: 0 wait states */ CSCR1 = 0x00000180; /* LCD: 0 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@ -70,7 +70,7 @@ void set_cpu_frequency(long frequency)
/* Refresh timer for bypass frequency */ /* Refresh timer for bypass frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
PLLCR = 0x10800200; /* Power down PLL, but keep CLSEL and CRSEL */ PLLCR = 0x10400200; /* Power down PLL, but keep CLSEL and CRSEL */
CSCR0 = 0x00000180; /* Flash: 0 wait states */ CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */ CSCR1 = 0x00000180; /* LCD: 0 wait states */
DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */