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imx31: Oops. Fix a misplaced comma in wmcodec-imx31.c. Add a couple parentheses in statment (just to be clearer). Should take care of things for now :).

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20444 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2009-03-22 02:27:20 +00:00
parent ba71cc540c
commit e48cece75c
3 changed files with 5 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

4
firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
View file

@ -53,8 +53,8 @@ void tick_start(unsigned int interval_in_ms)
* Compare interrupt enabled, * Compare interrupt enabled,
* Count from load value */ * Count from load value */
EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
(2640-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_OCIEN | ((2640-1) << EPITCR_PRESCALER_POS) | EPITCR_RLD |
EPITCR_ENMOD; EPITCR_OCIEN | EPITCR_ENMOD;
EPITLR1 = interval_in_ms*25; /* Count down from interval */ EPITLR1 = interval_in_ms*25; /* Count down from interval */
EPITCMPR1 = 0; /* Event when counter reaches 0 */ EPITCMPR1 = 0; /* Event when counter reaches 0 */

2
firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
View file

@ -77,7 +77,7 @@ bool _timer_set(long cycles, bool start)
* Reload from modulus register, * Reload from modulus register,
* Count from load value */ * Count from load value */
EPITCR2 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | EPITCR2 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
(1-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_ENMOD; ((1-1) << EPITCR_PRESCALER_POS) | EPITCR_RLD | EPITCR_ENMOD;
EPITLR2 = cycles; EPITLR2 = cycles;
/* Event when counter reaches 0 */ /* Event when counter reaches 0 */
EPITCMPR2 = 0; EPITCMPR2 = 0;

4
firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
View file

@ -55,8 +55,8 @@ void audiohw_init(void)
imx31_regmod32(&CCM_PDR1, imx31_regmod32(&CCM_PDR1,
((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) | ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) |
((5-1) << CCM_PDR1_SSI1_PODF_POS) | ((5-1) << CCM_PDR1_SSI1_PODF_POS) |
((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS), ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) |
((64-1) << CCM_PDR1_SSI2_PODF_POS) | ((64-1) << CCM_PDR1_SSI2_PODF_POS),
CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF |
CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF);