as3525v2: share more of system_init() between the 2 SoCs

Differences remaining:
    - list of peripherals reset
    - CGU_PROC isn't modified on as3525v2
    - CGU_PLLA bits aren't known, but we use a known setting for 240MHz

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24868 a1c6a512-1295-4272-9138-f99709370657

firmware/target/arm/as3525/clock-target.h

@@ -61,10 +61,21 @@
 /** ************ Change these to reconfigure clocking scheme *******************/
 #if CONFIG_CPU == AS3525v2
 
-/* PLL* registers differ from AS3525 */
+/* PLLA & PLLB registers differ from AS3525(v1)
+ * so we use a setting with a known frequency */
 #define AS3525_PLLA_FREQ        240000000
+#define AS3525_PLLA_SETTING     0x113B
 
-#else
+/* XXX: CGU_PROC seems to be different as well */
+#define AS3525_FCLK_PREDIV      0
+#define AS3525_FCLK_FREQ        AS3525_PLLA_FREQ
+
+/* XXX: CGU_PERI might also be different (i.e. no PCLK_DIV1_SEL), but if we use
+ * the same frequency for DRAM & PCLK it's not a problem as the bit is unset */
+#define AS3525_DRAM_FREQ        60000000    /* Initial DRAM frequency  */
+#define AS3525_PCLK_FREQ        AS3525_DRAM_FREQ/1
+
+#else /* AS3525v1 */
 
 /* PLL  frequencies and settings*/
 #define AS3525_PLLA_FREQ        248000000   /*124,82.7,62,49.6,41.3,35.4 */
@@ -77,18 +88,12 @@
 #define AS3525_PLLB_FREQ        384000000   /* allows 44.1kHz with 0.04% error*/
 #define AS3525_PLLB_SETTING     0x2630
 
-#endif  /* CONFIG_CPU == AS3525v2 */
-
 //#define AS3525_PLLA_FREQ        384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/
        /* FCLK_PREDIV->  *7/8 = 336MHz      168, 112, 84, 67.2, 56, 48, 42, 37.3*/
                       /* *6/8 = 288MHz      144, 96, 72, 57.6, 48, 41.1, */
                       /* *5/8 = 240MHz      120, 80, 60, 48, 40  */
 //#define AS3525_PLLA_SETTING     0x2630
 
-/*  PLLB not used at this time! */
-//#define AS3525_PLLB_FREQ
-//#define AS3525_PLLB_SETTING
-
 #define AS3525_FCLK_PREDIV    0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/
                                 /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */
 
@@ -96,6 +101,9 @@
 #define AS3525_DRAM_FREQ       62000000            /* Initial DRAM frequency  */
         /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */
 #define AS3525_PCLK_FREQ      AS3525_DRAM_FREQ/1   /* PCLK divided from DRAM freq */
+
+#endif  /* CONFIG_CPU == AS3525v2 */
+
 #define AS3525_DBOP_FREQ      AS3525_PCLK_FREQ/1   /* DBOP divided from PCLK freq */
 
 /** ****************************************************************************/

firmware/target/arm/as3525/system-as3525.c

@@ -258,27 +258,13 @@ void memory_init(void)
 void system_init(void)
 {
 #if CONFIG_CPU == AS3525v2
-    /* Init procedure isn't fully understood yet
-     * CCU_* registers differ from AS3525
-     */
-    unsigned int reset_loops = 640;
-
     CCU_SRC = 0x57D7BF0;
-    while(reset_loops--)
-        CCU_SRL = CCU_SRL_MAGIC_NUMBER;
-    CCU_SRC = CCU_SRL = 0;
-
-#ifdef BOOTLOADER   /* FIXME */
-    CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
-    CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2)
-                | 1; /* clk_in = PLLA */
-#endif
-
 #else
-    unsigned int reset_loops = 640;
-
     CCU_SRC = 0x1fffff0
         & ~CCU_SRC_IDE_EN; /* FIXME */
+#endif
+
+    unsigned int reset_loops = 640;
     while(reset_loops--)
         CCU_SRL = CCU_SRL_MAGIC_NUMBER;
     CCU_SRC = CCU_SRL = 0;
@@ -286,7 +272,9 @@ void system_init(void)
     CCU_SCON = 1; /* AHB master's priority configuration :
                      TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
 
+#if CONFIG_CPU == AS3525
     CGU_PROC = 0;           /* fclk 24 MHz */
+#endif
     CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
 
     CGU_PLLASUP = 0;        /* enable PLLA */
@@ -299,12 +287,15 @@ void system_init(void)
     while(!(CGU_INTCTRL & (1<<1)));           /* wait until PLLB is locked */
 #endif
 
+#if CONFIG_CPU == AS3525
     /*  Set FCLK frequency */
     CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
                 (AS3525_FCLK_PREDIV  << 2) |
                  AS3525_FCLK_SEL);
+#endif
+
     /*  Set PCLK frequency */
-    CGU_PERI = ((CGU_PERI & ~0x7F)  |       /* reset divider bits 0:6 */
+    CGU_PERI = ((CGU_PERI & ~0x7F)  |       /* reset divider & clksel bits */
                  (AS3525_PCLK_DIV0 << 2) |
                  (AS3525_PCLK_DIV1 << 6) |
                   AS3525_PCLK_SEL);
@@ -315,8 +306,6 @@ void system_init(void)
         "mcr p15, 0, r0, c1, c0   \n"
         : : : "r0" );
 
-#endif /* CONFIG_CPU == AS3525v2 */
-
 #ifdef BOOTLOADER
     sdram_init();
 #endif  /* BOOTLOADER */