mirror of
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Embryo of a SD driver for Sansav2
Debug code included, needed until the bootloader is ready git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18926 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré
parent
4c457afe89
commit
e1b4838481
4 changed files with 469 additions and 1 deletions
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@ -30,6 +30,7 @@
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#include "backlight-target.h"
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#include "as3525-codec.h"
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#include "common.h"
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#include "ata.h"
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int show_logo(void);
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void main(void)
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@ -53,6 +54,8 @@ void main(void)
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}
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printf("ID: %02X%02X%02X%02X%02X%02X%02X%02X", buf[7], buf[6], buf[5], buf[4], buf[3], buf[2], buf[1], buf[0]);
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ata_init();
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#ifdef SANSA_CLIP
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/* Use hardware scrolling */
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@ -330,6 +330,7 @@ target/arm/pnx0101/system-pnx0101.c
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#if CONFIG_CPU == AS3525
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target/arm/as3525/system-as3525.c
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target/arm/as3525/ata_sd_as3525.c
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#endif
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#if defined(CPU_PP)
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341
firmware/target/arm/as3525/ata_sd_as3525.c
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341
firmware/target/arm/as3525/ata_sd_as3525.c
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@ -0,0 +1,341 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
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#include "config.h" /* for HAVE_MULTIVOLUME */
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#include "as3525.h"
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#include "mmci.h"
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#include "panic.h"
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#include "stdbool.h"
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#include "ata.h"
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#define NAND_AS3525 0
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#define SD_AS3525 1
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static int pl180_base[2] = { NAND_FLASH_BASE, SD_MCI_BASE };
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/* ARM PL180 registers */
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#define MMC_POWER(i) (*(volatile unsigned long *) (pl180_base[i]+0x00))
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#define MMC_CLOCK(i) (*(volatile unsigned long *) (pl180_base[i]+0x04))
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#define MMC_ARGUMENT(i) (*(volatile unsigned long *) (pl180_base[i]+0x08))
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#define MMC_COMMAND(i) (*(volatile unsigned long *) (pl180_base[i]+0x0C))
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#define MMC_RESPCMD(i) (*(volatile unsigned long *) (pl180_base[i]+0x10))
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#define MMC_RESP0(i) (*(volatile unsigned long *) (pl180_base[i]+0x14))
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#define MMC_RESP1(i) (*(volatile unsigned long *) (pl180_base[i]+0x18))
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#define MMC_RESP2(i) (*(volatile unsigned long *) (pl180_base[i]+0x1C))
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#define MMC_RESP3(i) (*(volatile unsigned long *) (pl180_base[i]+0x20))
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#define MMC_DATACTRL(i) (*(volatile unsigned long *) (pl180_base[i]+0x2C))
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#define MMC_STATUS(i) (*(volatile unsigned long *) (pl180_base[i]+0x34))
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#define MMC_CLEAR(i) (*(volatile unsigned long *) (pl180_base[i]+0x38))
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#define MMC_MASK0(i) (*(volatile unsigned long *) (pl180_base[i]+0x3C))
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#define MMC_MASK1(i) (*(volatile unsigned long *) (pl180_base[i]+0x40))
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#define MMC_SELECT(i) (*(volatile unsigned long *) (pl180_base[i]+0x44))
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/* SD commands */
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#define GO_IDLE_STATE 0
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#define MMC_CMD_READ_CID 2
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#define SEND_IF_COND 8
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#define SEND_OP_COND 41
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#define APP_CMD 55
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/* command flags */
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#define MMC_NO_FLAGS (0<<0)
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#define MMC_RESP (1<<0)
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#define MMC_LONG_RESP (1<<1)
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#define MMC_ARG (1<<2)
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#ifdef BOOTLOADER
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#define DEBUG
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void reset_screen(void);
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void printf(const char *format, ...);
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#endif
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struct mmc_command
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{
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int cmd;
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int arg;
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int resp[4];
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int flags;
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};
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static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
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static void mci_set_clock_divider(const int drive, int divider)
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{
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int clock = MMC_CLOCK(drive);
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if(divider > 1)
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{
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/* use divide logic */
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clock &= ~MCI_CLK_BYPASS;
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/* convert divider to MMC_CLOCK logic */
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divider = (divider/2) - 1;
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if(divider >= 256)
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divider = 255;
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}
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else
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{
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/* bypass dividing logic */
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clock |= MCI_CLK_BYPASS;
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divider = 0;
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}
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MMC_CLOCK(drive) = clock | divider;
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mci_delay();
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}
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static int send_cmd(const int drive, struct mmc_command *cmd)
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{
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int val, status;
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while(MMC_STATUS(drive) & MCI_CMDACTIVE); /* useless */
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if(MMC_COMMAND(drive) & MCI_CPSM_ENABLE) /* clears existing command */
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{
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MMC_COMMAND(drive) = 0;
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mci_delay();
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}
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val = cmd->cmd | MCI_CPSM_ENABLE;
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if(cmd->flags & MMC_RESP)
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{
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val |= MCI_CPSM_RESPONSE;
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if(cmd->flags & MMC_LONG_RESP)
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val |= MCI_CPSM_LONGRSP;
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}
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MMC_CLEAR(drive) = 0x7ff;
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MMC_ARGUMENT(drive) = (cmd->flags & MMC_ARG) ? cmd->arg : 0;
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MMC_COMMAND(drive) = val;
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while(MMC_STATUS(drive) & MCI_CMDACTIVE);
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MMC_COMMAND(drive) = 0;
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MMC_ARGUMENT(drive) = ~0;
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do
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{
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status = MMC_STATUS(drive);
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if(cmd->flags & MMC_RESP)
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{
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if(status & MCI_CMDTIMEOUT)
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{
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if(cmd->cmd == SEND_IF_COND)
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break; /* SDHC test can fail */
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panicf("Response timeout");
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}
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else if(status & (MCI_CMDCRCFAIL|MCI_CMDRESPEND))
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{ /* resp received */
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cmd->resp[0] = MMC_RESP0(drive);
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if(cmd->flags & MMC_LONG_RESP)
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{
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cmd->resp[1] = MMC_RESP1(drive);
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cmd->resp[2] = MMC_RESP2(drive);
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cmd->resp[3] = MMC_RESP3(drive);
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}
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break;
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}
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}
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else
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if(status & MCI_CMDSENT)
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break;
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} while(1);
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MMC_CLEAR(drive) = 0x7ff;
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return status;
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}
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static void sd_init_card(const int drive)
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{
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struct mmc_command cmd_app, cmd_op_cond, cmd_idle, cmd_if_cond;
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int status;
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bool sdhc;
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#ifdef DEBUG
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reset_screen();
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printf("now - powered up");
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#endif
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cmd_idle.cmd = GO_IDLE_STATE;
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cmd_idle.arg = 0;
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cmd_idle.flags = MMC_NO_FLAGS;
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if(send_cmd(drive, &cmd_idle) != MCI_CMDSENT)
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panicf("goto idle failed!");
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#ifdef DEBUG
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else
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printf("now - idle");
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#endif
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mci_delay();
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cmd_if_cond.cmd = SEND_IF_COND;
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cmd_if_cond.arg = (1 /* 2.7-3.6V */ << 8) | 0xAA /* check pattern */;
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cmd_if_cond.flags = MMC_RESP | MMC_ARG;
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cmd_app.cmd = APP_CMD;
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cmd_app.flags = MMC_RESP | MMC_ARG;
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cmd_app.arg = 0; /* 31:16 RCA (0) , 15:0 stuff bits */
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cmd_op_cond.cmd = SEND_OP_COND;
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cmd_op_cond.flags = MMC_RESP | MMC_ARG;
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#ifdef DEBUG
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printf("now - card powering up");
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#endif
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sdhc = false;
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status = send_cmd(drive, &cmd_if_cond);
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if(status & (MCI_CMDCRCFAIL|MCI_CMDRESPEND))
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{
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if((cmd_if_cond.resp[0] & 0xFFF) == cmd_if_cond.arg)
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sdhc = true;
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#ifdef DEBUG
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else
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printf("Bad resp: %x",cmd_if_cond.arg);
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#endif
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}
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#ifdef DEBUG
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else
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printf("cmd_if_cond stat: 0x%x",status);
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printf("%s Capacity",sdhc?"High":"Normal");
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mci_delay();
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mci_delay();
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mci_delay();
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#endif
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#ifdef DEBUG
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int loop = 0;
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#endif
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do {
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mci_delay();
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mci_delay();
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#ifdef DEBUG
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reset_screen();
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printf("Loop number #%d", ++loop);
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#endif
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/* app_cmd */
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status = send_cmd(drive, &cmd_app);
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if( !(status & (MCI_CMDCRCFAIL|MCI_CMDRESPEND)) ||
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!(cmd_app.resp[0] & (1<<5)) )
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{
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panicf("app_cmd failed");
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}
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cmd_op_cond.arg = sdhc ? 0x40FF8000 : (8<<0x14); /* ocr */
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status = send_cmd(drive, &cmd_op_cond);
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if(!(status & (MCI_CMDCRCFAIL|MCI_CMDRESPEND)))
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panicf("cmd_op_cond failed");
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#ifdef DEBUG
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printf("OP COND: 0x%.8x", cmd_op_cond.resp[0]);
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#endif
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} while(!(cmd_op_cond.resp[0] & (1<<31))); /* until card is powered up */
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#ifdef DEBUG
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printf("now - card ready !");
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#endif
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}
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static void init_pl180_controller(const int drive)
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{
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MMC_COMMAND(drive) = MMC_DATACTRL(drive) = 0;
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MMC_CLEAR(drive) = 0x7ff;
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MMC_MASK0(drive) = MMC_MASK1(drive) = 0; /* disable all interrupts */
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MMC_POWER(drive) = MCI_PWR_UP | (10 /*voltage*/ << 2); /* use OF voltage */
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mci_delay();
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MMC_POWER(drive) |= MCI_PWR_ON;
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mci_delay();
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MMC_SELECT(drive) = 0;
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MMC_CLOCK(drive) = MCI_CLK_ENABLE;
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MMC_CLOCK(drive) &= ~MCI_CLK_PWRSAVE;
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/* set MCLK divider */
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mci_set_clock_divider(drive, 200);
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}
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int ata_init(void)
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{
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/* reset peripherals */
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CCU_SRC =
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#ifdef HAVE_MULTIVOLUME
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CCU_SRC_SDMCI_EN |
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#endif
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CCU_SRC_NAF_EN | CCU_SRC_IDE_EN | CCU_SRC_IDE_AHB_EN | CCU_SRC_MST_EN;
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CCU_SRL = CCU_SRL_MAGIC_NUMBER;
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CCU_SRL = 0;
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GPIOC_DIR &= ~(1<<1);
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if(GPIOC_PIN(1))
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CCU_SPARE1 |= 4; /* sets bit 3 of undocumented register */
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else
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CCU_SPARE1 &= ~4; /* or clear it */
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CGU_IDE = (1<<7)|(1<<6); /* enable, 24MHz clock */
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CGU_MEMSTICK = (1<<8); /* enable, 24MHz clock */
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CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
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#ifdef HAVE_MULTIVOLUME
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CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
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#endif
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CCU_IO &= ~8; /* bits 3:2 = 01, xpd is SD interface */
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CCU_IO |= 4;
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init_pl180_controller(NAND_AS3525);
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sd_init_card(NAND_AS3525);
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#ifdef HAVE_MULTIVOLUME
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init_pl180_controller(SD_AS3525);
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sd_init_card(SD_AS3525);
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#endif
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return 0;
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}
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int ata_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
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{
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(void)start;
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(void)count;
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(void)buf;
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return 0; /* TODO */
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}
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int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf)
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{
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(void)start;
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(void)count;
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(void)buf;
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return 0; /* TODO */
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}
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123
firmware/target/arm/as3525/mmci.h
Normal file
123
firmware/target/arm/as3525/mmci.h
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/*
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* linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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//#define MMCIPOWER 0x000
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#define MCI_PWR_OFF 0x00
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#define MCI_PWR_UP 0x02
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#define MCI_PWR_ON 0x03
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#define MCI_OD (1 << 6)
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#define MCI_ROD (1 << 7)
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//#define MMCICLOCK 0x004
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#define MCI_CLK_ENABLE (1 << 8)
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#define MCI_CLK_PWRSAVE (1 << 9)
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#define MCI_CLK_BYPASS (1 << 10)
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#define MCI_WIDEBUS (1 << 11)
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//#define MMCIARGUMENT 0x008
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//#define MMCICOMMAND 0x00c
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#define MCI_CPSM_RESPONSE (1 << 6)
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#define MCI_CPSM_LONGRSP (1 << 7)
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#define MCI_CPSM_INTERRUPT (1 << 8)
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#define MCI_CPSM_PENDING (1 << 9)
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#define MCI_CPSM_ENABLE (1 << 10)
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#if 0
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#define MMCIRESPCMD 0x010
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#define MMCIRESPONSE0 0x014
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#define MMCIRESPONSE1 0x018
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#define MMCIRESPONSE2 0x01c
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#define MMCIRESPONSE3 0x020
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#define MMCIDATATIMER 0x024
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#define MMCIDATALENGTH 0x028
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#define MMCIDATACTRL 0x02c
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#endif
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#define MCI_DPSM_ENABLE (1 << 0)
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#define MCI_DPSM_DIRECTION (1 << 1)
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#define MCI_DPSM_MODE (1 << 2)
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#define MCI_DPSM_DMAENABLE (1 << 3)
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//#define MMCIDATACNT 0x030
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//#define MMCISTATUS 0x034
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#define MCI_CMDCRCFAIL (1 << 0)
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#define MCI_DATACRCFAIL (1 << 1)
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#define MCI_CMDTIMEOUT (1 << 2)
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#define MCI_DATATIMEOUT (1 << 3)
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#define MCI_TXUNDERRUN (1 << 4)
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#define MCI_RXOVERRUN (1 << 5)
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_DATAEND (1 << 8)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_TXACTIVE (1 << 12)
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#define MCI_RXACTIVE (1 << 13)
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#define MCI_TXFIFOHALFEMPTY (1 << 14)
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#define MCI_RXFIFOHALFFULL (1 << 15)
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#define MCI_TXFIFOFULL (1 << 16)
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#define MCI_RXFIFOFULL (1 << 17)
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#define MCI_TXFIFOEMPTY (1 << 18)
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#define MCI_RXFIFOEMPTY (1 << 19)
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#define MCI_TXDATAAVLBL (1 << 20)
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#define MCI_RXDATAAVLBL (1 << 21)
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//#define MMCICLEAR 0x038
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#define MCI_CMDCRCFAILCLR (1 << 0)
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#define MCI_DATACRCFAILCLR (1 << 1)
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#define MCI_CMDTIMEOUTCLR (1 << 2)
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#define MCI_DATATIMEOUTCLR (1 << 3)
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#define MCI_TXUNDERRUNCLR (1 << 4)
|
||||
#define MCI_RXOVERRUNCLR (1 << 5)
|
||||
#define MCI_CMDRESPENDCLR (1 << 6)
|
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#define MCI_CMDSENTCLR (1 << 7)
|
||||
#define MCI_DATAENDCLR (1 << 8)
|
||||
#define MCI_DATABLOCKENDCLR (1 << 10)
|
||||
|
||||
//#define MMCIMASK0 0x03c
|
||||
#define MCI_CMDCRCFAILMASK (1 << 0)
|
||||
#define MCI_DATACRCFAILMASK (1 << 1)
|
||||
#define MCI_CMDTIMEOUTMASK (1 << 2)
|
||||
#define MCI_DATATIMEOUTMASK (1 << 3)
|
||||
#define MCI_TXUNDERRUNMASK (1 << 4)
|
||||
#define MCI_RXOVERRUNMASK (1 << 5)
|
||||
#define MCI_CMDRESPENDMASK (1 << 6)
|
||||
#define MCI_CMDSENTMASK (1 << 7)
|
||||
#define MCI_DATAENDMASK (1 << 8)
|
||||
#define MCI_DATABLOCKENDMASK (1 << 10)
|
||||
#define MCI_CMDACTIVEMASK (1 << 11)
|
||||
#define MCI_TXACTIVEMASK (1 << 12)
|
||||
#define MCI_RXACTIVEMASK (1 << 13)
|
||||
#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
|
||||
#define MCI_RXFIFOHALFFULLMASK (1 << 15)
|
||||
#define MCI_TXFIFOFULLMASK (1 << 16)
|
||||
#define MCI_RXFIFOFULLMASK (1 << 17)
|
||||
#define MCI_TXFIFOEMPTYMASK (1 << 18)
|
||||
#define MCI_RXFIFOEMPTYMASK (1 << 19)
|
||||
#define MCI_TXDATAAVLBLMASK (1 << 20)
|
||||
#define MCI_RXDATAAVLBLMASK (1 << 21)
|
||||
|
||||
#if 0
|
||||
#define MMCIMASK1 0x040
|
||||
#define MMCIFIFOCNT 0x048
|
||||
#define MMCIFIFO 0x080 /* to 0x0bc */
|
||||
#endif
|
||||
|
||||
#define MCI_IRQENABLE \
|
||||
(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
|
||||
MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
|
||||
MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
|
||||
|
||||
/*
|
||||
* The size of the FIFO in bytes.
|
||||
*/
|
||||
#define MCI_FIFOSIZE (16*4)
|
||||
|
||||
#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
|
||||
|
||||
#define NR_SG 16
|
||||
Loading…
Add table
Add a link
Reference in a new issue