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xduoox3: Set PLL0 to 480MHz, not 492.

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PLL0 Needs to be a multiple of 48MHz for sane USB operation!

(Indeed, "typical" clock for this part is 528, but that seems a
 waste of power)

Also fixes a minor bugaboo in the jz4670 usb divisor calculation
that won't matter until we enable reclocking

Change-Id: I40b1fd1ae48871e50885981ccc8b01feb711b9a5
This commit is contained in:
Solomon Peachy 2020-08-06 22:17:23 -04:00
parent f554c78734
commit e0bb30a1bd
2 changed files with 2 additions and 2 deletions
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2
firmware/target/mips/ingenic_jz47xx/system-jz4760.c
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@ -478,7 +478,7 @@ static void pll0_init(unsigned int freq)
* Init USB Host clock, pllout2 must be n*48MHz
* For JZ4760b UHC - River.
*/
usbdiv = (cfcr & CPCCR_PCS) ? CPU_FREQ : (CPU_FREQ / 2);
usbdiv = (cfcr & CPCCR_PCS) ? freq : (freq / 2);
REG_CPM_UHCCDR = usbdiv / 48000000 - 1;
/* init PLL */