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Split up DMA and ATA, but don't enable it (yet).

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17386 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere 2008-05-05 15:47:26 +00:00
parent 6d12109ef7
commit e025cb1c38
5 changed files with 187 additions and 73 deletions
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70
firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c
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@ -92,79 +92,9 @@ bool ata_is_coldstart(void)
return true;
}
#if 0 /* Disabled as device crashes; probably due to SDRAM addresses aren't 32-bit aligned */
#define CS1_START 0x50000000
#define DEST_ADDR (ATA_IOBASE-CS1_START)
static struct wakeup transfer_completion_signal;
void MTC0(void)
{
IO_INTC_IRQ1 = 1 << IRQ_MTC0;
wakeup_signal(&transfer_completion_signal);
}
void copy_read_sectors(unsigned char* buf, int wordcount)
{
bool lasthalfword = false;
unsigned short tmp;
if(wordcount < 16)
{
_copy_read_sectors(buf, wordcount);
return;
}
else if((unsigned long)buf % 32) /* Not 32-byte aligned */
{
unsigned char* bufend = buf + ((unsigned long)buf % 32);
if( ((unsigned long)buf % 32) % 2 )
lasthalfword = true;
wordcount -= ((unsigned long)buf % 32) / 2;
do
{
tmp = ATA_DATA;
*buf++ = tmp >> 8;
*buf++ = tmp & 0xff;
} while (buf < bufend); /* tail loop is faster */
}
IO_SDRAM_SDDMASEL = 0x0830; /* 32-byte burst mode transfer */
IO_EMIF_AHBADDH = ((unsigned)buf >> 16) & ~(1 << 15); /* Set variable address */
IO_EMIF_AHBADDL = (unsigned)buf & 0xFFFF;
IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */
IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF;
IO_EMIF_DMASIZE = wordcount*2;
IO_EMIF_DMACTL = 3; /* Select MTC->AHB and start transfer */
//wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
while(IO_EMIF_DMACTL & 1)
nop;
if(lasthalfword)
{
*buf += wordcount * 2;
tmp = ATA_DATA;
*buf++ = tmp >> 8;
*buf++ = tmp & 0xff;
}
}
void copy_write_sectors(const unsigned char* buf, int wordcount)
{
IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
IO_SDRAM_SDDMASEL = 0x0820; /* Temporarily set to standard value */
IO_EMIF_AHBADDH = ((int)buf >> 16) & ~(1 << 15); /* Set variable address */
IO_EMIF_AHBADDL = (int)buf & 0xFFFF;
IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */
IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF;
IO_EMIF_DMASIZE = wordcount;
IO_EMIF_DMACTL = 1; /* Select AHB->MTC and start transfer */
wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
}
#endif
void ata_device_init(void)
{
IO_INTC_EINT1 |= INTR_EINT1_EXT2; /* enable GIO2 interrupt */
#if 0
IO_INTC_EINT1 |= 1 << IRQ_MTC0; /* enable MTC interrupt */
wakeup_init(&transfer_completion_signal);
#endif
//TODO: mimic OF inits...
return;
}