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Third try fixing MIPS cache code

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Changing this to be a pure discard operation after discussion on IRC

Change-Id: I62955ae7975fdbbfd9eef376476042a36fe3d95a
This commit is contained in:
Aidan MacDonald 2021-03-04 00:53:16 +00:00 • committed by Solomon Peachy
parent b82298ae2c
commit de53965e3f
1 changed files with 1 additions and 14 deletions
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15
firmware/target/mips/mmu-mips.c
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@ -222,20 +222,7 @@ void discard_dcache_range(const void *base, unsigned int size)
char *ptr = CACHEALIGN_DOWN((char*)base);
char *end = CACHEALIGN_UP((char*)base + size);
if(ptr != base) {
/* Start of region not cache aligned */
__CACHE_OP(DCHitWBInv, ptr);
ptr += CACHEALIGN_SIZE;
}
if(base+size != end) {
/* End of region not cache aligned */
end -= CACHEALIGN_SIZE;
__CACHE_OP(DCHitWBInv, end);
}
/* Interior of region is safe to discard */
for(; ptr <= end; ptr += CACHEALIGN_SIZE)
for(; ptr != end; ptr += CACHEALIGN_SIZE)
__CACHE_OP(DCHitInv, ptr);
SYNC_WB();