len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2025-12-10 21:55:10 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions

MIPS: set load address of .iram to the start of .bss so RAM doesn't get wasted

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20741 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere 2009-04-19 14:10:59 +00:00
parent 42c7fb6b8b
commit dc8db2a820
2 changed files with 22 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

7
firmware/target/mips/ingenic_jz47xx/app.lds
View file

@ -70,7 +70,10 @@ SECTIONS
. = ALIGN(4);
.iram IRAMORIG:
/* Set the load address of .iram at the same address as .bss
* so RAM won't be wasted as .iram in the end will get copied
* to IRAM. */
.iram IRAMORIG: AT (_edata)
{
_iramstart = .;
*(.vectors.1);
@ -88,7 +91,7 @@ SECTIONS
KEEP(*(.vectors))
*(.vectors);
_iramend = .;
} > IRAM AT> DRAM
} > IRAM
_iramcopy = LOADADDR(.iram);
. = ALIGN(4);

32
firmware/target/mips/ingenic_jz47xx/crt0.S
View file

@ -120,6 +120,23 @@ _init_cache_loop:
mtc0 t0, C0_CONFIG
nop
/*
----------------------------------------------------
Copy IRAM section
* copy IRAM first before BSS gets cleared, as both
have the same address
----------------------------------------------------
*/
la t0, _iramcopy
la t1, _iramstart
la t2, _iramend
_init_iram_loop:
lw t3, 0(t0)
sw t3, 0(t1)
addiu t1, 4
bne t1, t2, _init_iram_loop
addiu t0, 4
/*
----------------------------------------------------
Clear BSS section
@ -143,21 +160,6 @@ _init_ibss_loop:
sw zero, 0(t0)
bne t0, t1, _init_ibss_loop
addiu t0, 4
/*
----------------------------------------------------
Copy IRAM section
----------------------------------------------------
*/
la t0, _iramcopy
la t1, _iramstart
la t2, _iramend
_init_iram_loop:
lw t3, 0(t0)
sw t3, 0(t1)
addiu t1, 4
bne t1, t2, _init_iram_loop
addiu t0, 4
/*
----------------------------------------------------