diff --git a/firmware/target/mips/ingenic_jz47xx/app.lds b/firmware/target/mips/ingenic_jz47xx/app.lds
index bec8671ec9..8177db794f 100644
--- a/firmware/target/mips/ingenic_jz47xx/app.lds
+++ b/firmware/target/mips/ingenic_jz47xx/app.lds
@@ -66,7 +66,7 @@ SECTIONS
         KEEP(*(.vectors.4));
         KEEP(*(.vectors));
 
-        *(.icode);
+        *(.icode*);
         *(.irodata);
         *(.idata);
         KEEP(*(.vectors))
diff --git a/firmware/target/mips/ingenic_jz47xx/boot.lds b/firmware/target/mips/ingenic_jz47xx/boot.lds
index 9492050695..7b53272058 100644
--- a/firmware/target/mips/ingenic_jz47xx/boot.lds
+++ b/firmware/target/mips/ingenic_jz47xx/boot.lds
@@ -58,7 +58,7 @@ SECTIONS
         KEEP(*(.vectors.4));
         KEEP(*(.vectors));
 
-        *(.icode);
+        *(.icode*);
         *(.irodata);
         *(.idata);
         KEEP(*(.vectors*))
diff --git a/firmware/target/mips/ingenic_x1000/app.lds b/firmware/target/mips/ingenic_x1000/app.lds
index 0f6352b8ee..bcfb3b28cf 100644
--- a/firmware/target/mips/ingenic_x1000/app.lds
+++ b/firmware/target/mips/ingenic_x1000/app.lds
@@ -63,7 +63,7 @@ SECTIONS
         KEEP(*(.vectors.4));
         KEEP(*(.vectors));
 
-        *(.icode);
+        *(.icode*);
         *(.irodata);
         *(.idata);
         _iramend = .;
diff --git a/firmware/target/mips/ingenic_x1000/spl.lds b/firmware/target/mips/ingenic_x1000/spl.lds
index ab4a2720f3..f11fd2cf3b 100644
--- a/firmware/target/mips/ingenic_x1000/spl.lds
+++ b/firmware/target/mips/ingenic_x1000/spl.lds
@@ -26,6 +26,7 @@ SECTIONS
     {
         *(.init.text);
         *(.text*);
+        *(.icode*);
     } > TCSM
 
     . = ALIGN(4);
diff --git a/firmware/target/mips/ingenic_x1000/system-target.h b/firmware/target/mips/ingenic_x1000/system-target.h
index e5e48e382b..13024584d3 100644
--- a/firmware/target/mips/ingenic_x1000/system-target.h
+++ b/firmware/target/mips/ingenic_x1000/system-target.h
@@ -28,15 +28,6 @@
 #define CACHEALIGN_BITS 5
 #define CACHE_SIZE      (16*1024)
 
-#ifdef BOOTLOADER_SPL
-/* This saves ~200 bytes in the SPL by allowing -ffunction-sections to split
- * up the cache management functions, most of which aren't called by the SPL.
- * If they are placed in .icode, then they all end up in one section and the
- * linker can't discard the unused functions.
- */
-# define MIPS_CACHEFUNC_ATTR
-#endif
-
 #ifdef DEBUG
 /* Define this to get CPU idle stats, visible in the debug menu. */
 # define X1000_CPUIDLE_STATS
diff --git a/firmware/target/mips/mmu-mips.h b/firmware/target/mips/mmu-mips.h
index b54807f060..b8f5ff0143 100644
--- a/firmware/target/mips/mmu-mips.h
+++ b/firmware/target/mips/mmu-mips.h
@@ -28,33 +28,32 @@
  * called safely eg. by the bootloader or RoLo, which need to flush the
  * cache before jumping to the loaded binary.
  */
-#ifndef MIPS_CACHEFUNC_ATTR
-# define MIPS_CACHEFUNC_ATTR  __attribute__((section(".icode")))
-#endif
+#define MIPS_CACHEFUNC_API(ret, name, args) \
+    ret name args __attribute__((section( ".icode." #name )))
 
 void map_address(unsigned long virtual, unsigned long physical,
                  unsigned long length, unsigned int cache_flags);
 void mmu_init(void);
 
 /* Commits entire DCache */
-void commit_dcache(void) MIPS_CACHEFUNC_ATTR;
+MIPS_CACHEFUNC_API(void, commit_dcache, (void));
 /* Commit and discard entire DCache, will do writeback */
-void commit_discard_dcache(void) MIPS_CACHEFUNC_ATTR;
+MIPS_CACHEFUNC_API(void, commit_discard_dcache, (void));
 
 /* Write DCache back to RAM for the given range and remove cache lines
  * from DCache afterwards */
-void commit_discard_dcache_range(const void *base, unsigned int size) MIPS_CACHEFUNC_ATTR;
+MIPS_CACHEFUNC_API(void, commit_discard_dcache_range, (const void *base, unsigned int size));
 
 /* Write DCache back to RAM for the given range */
-void commit_dcache_range(const void *base, unsigned int size) MIPS_CACHEFUNC_ATTR;
+MIPS_CACHEFUNC_API(void, commit_dcache_range, (const void *base, unsigned int size));
 
 /*
  * Remove cache lines for the given range from DCache
  * will *NOT* do write back except for buffer edges not on a line boundary
  */
-void discard_dcache_range(const void *base, unsigned int size) MIPS_CACHEFUNC_ATTR;
+MIPS_CACHEFUNC_API(void, discard_dcache_range, (const void *base, unsigned int size));
 
 /* Discards the entire ICache, and commit+discards the entire DCache */
-void commit_discard_idcache(void) MIPS_CACHEFUNC_ATTR;
+MIPS_CACHEFUNC_API(void, commit_discard_idcache, (void));
 
 #endif /* __MMU_MIPS_INCLUDE_H */