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Meizu M6 SP: make bootloader compile and run again
* don't use DRAM yet in the bootloader linker script * add header files for the ftl and nand * update svn:keywords git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23347 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Bertrik Sikken
parent
6290f78177
commit
d2827996af
5 changed files with 481 additions and 371 deletions
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@ -58,6 +58,9 @@
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#define CONFIG_NAND NAND_SAMSUNG
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#define CONFIG_NAND NAND_SAMSUNG
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/* The NAND flash has 2048-byte sectors, and is our only storage */
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#define SECTOR_SIZE 2048
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/* LCD dimensions */
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/* LCD dimensions */
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#define LCD_WIDTH 240
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#define LCD_WIDTH 240
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#define LCD_HEIGHT 320
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#define LCD_HEIGHT 320
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@ -90,11 +90,13 @@ SECTIONS
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_fiqstackend = .;
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_fiqstackend = .;
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} > IRAM
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} > IRAM
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. = DRAMORIG;
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#ifdef IPOD_NANO2G
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/* The bss section is too large for IRAM - we just move it 12MB into the
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/* The bss section is too large for IRAM - we just move it 12MB into the
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DRAM */
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DRAM */
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. += (12*1024*1024) {
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. = DRAMORIG;
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#endif
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.bss . + (12*1024*1024): {
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.bss :{
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_edata = .;
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_edata = .;
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*(.bss*);
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*(.bss*);
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*(.ibss);
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*(.ibss);
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@ -102,5 +104,9 @@ SECTIONS
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*(COMMON);
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*(COMMON);
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. = ALIGN(0x4);
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. = ALIGN(0x4);
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_end = .;
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_end = .;
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#ifdef IPOD_NANO2G
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} > DRAM
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} > DRAM
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#else /* other targets don't have DRAM set up yet */
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} > IRAM
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#endif
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}
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}
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45
firmware/target/arm/s5l8700/meizu-m6sp/ftl-target.h
Normal file
45
firmware/target/arm/s5l8700/meizu-m6sp/ftl-target.h
Normal file
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@ -0,0 +1,45 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __FTL_TARGET_H__
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#define __FTL_TARGET_H__
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#include "config.h"
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#include "inttypes.h"
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#ifdef BOOTLOADER
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/* Bootloaders don't need write access */
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#define FTL_READONLY
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#endif
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/* Pointer to an info structure regarding the flash type used */
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const struct nand_device_info_type* ftl_nand_type;
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/* Number of banks we detected a chip on */
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uint32_t ftl_banks;
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uint32_t ftl_init(void);
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uint32_t ftl_read(uint32_t sector, uint32_t count, void* buffer);
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uint32_t ftl_write(uint32_t sector, uint32_t count, const void* buffer);
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uint32_t ftl_sync(void);
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#endif
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@ -19,12 +19,12 @@
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*
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*
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****************************************************************************/
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****************************************************************************/
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#include <inttypes.h>
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#include <inttypes.h>
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#include "config.h"
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#include "config.h"
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#include "s5l8700.h"
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#include "s5l8700.h"
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#include "lcd.h"
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#include "lcd.h"
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/* LCD driver for the Meizu M6 SP using the CLCD controller in the S5L8700
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/* LCD driver for the Meizu M6 SP using the CLCD controller in the S5L8700
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The Meizu M6 SP can have two different LCDs, the S6D0139 and another
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The Meizu M6 SP can have two different LCDs, the S6D0139 and another
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@ -40,10 +40,10 @@
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*/
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*/
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/* LCD SPI connections */
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/* LCD SPI connections */
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#define LCD_SPI_SSn (1<<1) /* on PDAT7 */
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#define LCD_SPI_SSn (1<<1) /* on PDAT7 */
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#define LCD_SPI_MISO (1<<2) /* on PDAT3 */
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#define LCD_SPI_MISO (1<<2) /* on PDAT3 */
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#define LCD_SPI_MOSI (1<<6) /* on PDAT3 */
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#define LCD_SPI_MOSI (1<<6) /* on PDAT3 */
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#define LCD_SPI_SCLK (1<<7) /* on PDAT3 */
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#define LCD_SPI_SCLK (1<<7) /* on PDAT3 */
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/* LCD SPI communication definitions */
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/* LCD SPI communication definitions */
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@ -51,317 +51,317 @@
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#define LCD_SPI_INDEX_WRITE (LCD_SPI_DEVICE_ID|0)
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#define LCD_SPI_INDEX_WRITE (LCD_SPI_DEVICE_ID|0)
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#define LCD_SPI_STATUS_READ (LCD_SPI_DEVICE_ID|1)
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#define LCD_SPI_STATUS_READ (LCD_SPI_DEVICE_ID|1)
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#define LCD_SPI_DATA_WRITE (LCD_SPI_DEVICE_ID|2)
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#define LCD_SPI_DATA_WRITE (LCD_SPI_DEVICE_ID|2)
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#define LCD_SPI_DATA_READ (LCD_SPI_DEVICE_ID|3)
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#define LCD_SPI_DATA_READ (LCD_SPI_DEVICE_ID|3)
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#define LCD_TYPE1_ID 0x139 /* id for LCD type S6D0139 */
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#define LCD_TYPE1_ID 0x139 /* id for LCD type S6D0139 */
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static int lcd_type = 0;
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static int lcd_type = 0;
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/* simple and crude delay */
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/* simple and crude delay */
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static void lcd_delay(int count)
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static void lcd_delay(int count)
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{
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{
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volatile int i;
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volatile int i;
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for (i = 0; i < count; i++);
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for (i = 0; i < count; i++);
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}
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}
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/* write 'data_out' of length 'bits' over SPI and return received data */
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/* write 'data_out' of length 'bits' over SPI and return received data */
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static unsigned int lcd_spi_transfer(int bits, unsigned int data_out)
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static unsigned int lcd_spi_transfer(int bits, unsigned int data_out)
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{
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{
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unsigned int data_in = 0;
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unsigned int data_in = 0;
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/* SSn active */
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PDAT7 &= ~LCD_SPI_SSn;
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lcd_delay(10);
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/* send and receive data */
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while (bits--) {
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/* CLK low */
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PDAT3 &= ~LCD_SPI_SCLK;
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/* set MOSI */
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if (data_out & (1 << bits)) {
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PDAT3 |= LCD_SPI_MOSI;
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}
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else {
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PDAT3 &= ~LCD_SPI_MOSI;
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}
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/* delay */
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lcd_delay(10);
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/* sample MISO */
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data_in <<= 1;
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if (PDAT3 & LCD_SPI_MISO) {
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data_in |= 1;
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}
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/* CLK high */
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PDAT3 |= LCD_SPI_SCLK;
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/* delay */
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lcd_delay(10);
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}
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/* SSn inactive */
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PDAT7 |= LCD_SPI_SSn;
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lcd_delay(10);
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return data_in;
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}
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/* initialize the lcd SPI port interface */
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static void lcd_spi_init(void)
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{
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/* configure SSn (P7.1) as output */
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PCON7 = (PCON7 & ~0x000000F0) | 0x00000010;
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/* configure MISO (P3.2) input, MOSI (P3.6) output, SCLK (P3.7) output */
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PCON3 = (PCON3 & ~0xFF000F00) | 0x11000000;
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/* set all outputs high */
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/* SSn active */
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PDAT7 |= LCD_SPI_SSn;
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PDAT7 &= ~LCD_SPI_SSn;
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PDAT3 |= (LCD_SPI_MOSI | LCD_SPI_SCLK);
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lcd_delay(10);
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}
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/* send and receive data */
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/* read LCD identification word over SPI */
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while (bits--) {
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static unsigned int lcd_read_reg(unsigned reg)
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/* CLK low */
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{
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PDAT3 &= ~LCD_SPI_SCLK;
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unsigned int data;
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/* set MOSI */
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if (data_out & (1 << bits)) {
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PDAT3 |= LCD_SPI_MOSI;
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}
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else {
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PDAT3 &= ~LCD_SPI_MOSI;
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}
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/* delay */
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lcd_delay(10);
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/* sample MISO */
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data_in <<= 1;
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if (PDAT3 & LCD_SPI_MISO) {
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data_in |= 1;
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}
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/* CLK high */
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PDAT3 |= LCD_SPI_SCLK;
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/* delay */
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lcd_delay(10);
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}
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/* SSn inactive */
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PDAT7 |= LCD_SPI_SSn;
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lcd_delay(10);
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return data_in;
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}
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/* initialize the lcd SPI port interface */
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static void lcd_spi_init(void)
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{
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/* configure SSn (P7.1) as output */
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PCON7 = (PCON7 & ~0x000000F0) | 0x00000010;
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/* configure MISO (P3.2) input, MOSI (P3.6) output, SCLK (P3.7) output */
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PCON3 = (PCON3 & ~0xFF000F00) | 0x11000000;
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/* set all outputs high */
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PDAT7 |= LCD_SPI_SSn;
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PDAT3 |= (LCD_SPI_MOSI | LCD_SPI_SCLK);
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}
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/* read LCD identification word over SPI */
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static unsigned int lcd_read_reg(unsigned reg)
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{
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unsigned int data;
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lcd_spi_transfer(24, (LCD_SPI_INDEX_WRITE << 16) | reg);
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lcd_spi_transfer(24, (LCD_SPI_INDEX_WRITE << 16) | reg);
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data = lcd_spi_transfer(24, (LCD_SPI_DATA_READ << 16));
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data = lcd_spi_transfer(24, (LCD_SPI_DATA_READ << 16));
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return data & 0xFFFF;
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return data & 0xFFFF;
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}
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}
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/* write LCD register over SPI */
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/* write LCD register over SPI */
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static void lcd_write_reg(unsigned char reg, unsigned int data)
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static void lcd_write_reg(unsigned char reg, unsigned int data)
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{
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{
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lcd_spi_transfer(24, (LCD_SPI_INDEX_WRITE << 16) | reg);
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lcd_spi_transfer(24, (LCD_SPI_INDEX_WRITE << 16) | reg);
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lcd_spi_transfer(24, (LCD_SPI_DATA_WRITE << 16) | data);
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lcd_spi_transfer(24, (LCD_SPI_DATA_WRITE << 16) | data);
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}
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}
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/* enable/disable clock signals towards the lcd */
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static void lcd_controller_power(bool on)
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{
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if (on) {
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LCDCON1 |= 0x80003;
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}
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else {
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LCDCON1 &= ~0x80003;
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}
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}
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/* lcd init configuration for lcd type 1 */
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static void lcd_init1(void)
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{
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lcd_write_reg(0x07, 0x0000); /* display control */
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lcd_write_reg(0x13, 0x0000); /* power control 3 */
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lcd_delay(166670);
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lcd_write_reg(0x11, 0x3304); /* power control 2 */
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lcd_write_reg(0x14, 0x1300); /* power control 4 */
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lcd_write_reg(0x10, 0x1A20); /* power control 1 */
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lcd_write_reg(0x13, 0x0040); /* power control 3 */
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lcd_delay(833350);
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lcd_write_reg(0x13, 0x0060); /* power control 3 */
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lcd_write_reg(0x13, 0x0070); /* power control 3 */
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lcd_delay(3333400);
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lcd_write_reg(0x01, 0x0127); /* driver output control */
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lcd_write_reg(0x02, 0x0700); /* lcd driving waveform control */
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lcd_write_reg(0x03, 0x1030); /* entry mode */
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lcd_write_reg(0x08, 0x0208); /* blank period control 1 */
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lcd_write_reg(0x0B, 0x0620); /* frame cycle control */
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lcd_write_reg(0x0C, 0x0110); /* external interface control */
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lcd_write_reg(0x30, 0x0120); /* gamma control 1 */
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lcd_write_reg(0x31, 0x0117); /* gamma control 2 */
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lcd_write_reg(0x32, 0x0000); /* gamma control 3 */
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lcd_write_reg(0x33, 0x0305); /* gamma control 4 */
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lcd_write_reg(0x34, 0x0717); /* gamma control 5 */
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lcd_write_reg(0x35, 0x0124); /* gamma control 6 */
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lcd_write_reg(0x36, 0x0706); /* gamma control 7 */
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lcd_write_reg(0x37, 0x0503); /* gamma control 8 */
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lcd_write_reg(0x38, 0x1F03); /* gamma control 9 */
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lcd_write_reg(0x39, 0x0009); /* gamma control 10 */
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lcd_write_reg(0x40, 0x0000); /* gate scan position */
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lcd_write_reg(0x41, 0x0000); /* vertical scroll control */
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lcd_write_reg(0x42, 0x013F); /* 1st screen driving position (end) */
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lcd_write_reg(0x43, 0x0000); /* 1st screen driving position (start) */
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lcd_write_reg(0x44, 0x013F); /* 2nd screen driving position (end) */
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lcd_write_reg(0x45, 0x0000); /* 2nd screen driving position (start) */
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lcd_write_reg(0x46, 0xEF00); /* horizontal window address */
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lcd_write_reg(0x47, 0x013F); /* vertical window address (end) */
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lcd_write_reg(0x48, 0x0000); /* vertical window address (start) */
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lcd_write_reg(0x07, 0x0015); /* display control */
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lcd_delay(500000);
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lcd_write_reg(0x07, 0x0017); /* display control */
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lcd_write_reg(0x20, 0x0000); /* RAM address set (low part) */
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lcd_write_reg(0x21, 0x0000); /* RAM address set (high part) */
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lcd_write_reg(0x22, 0x0000); /* write data to GRAM */
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}
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/* lcd init configuration for lcd type 2 */
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static void lcd_init2(void)
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{
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lcd_write_reg(0x07, 0x0000);
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lcd_write_reg(0x12, 0x0000);
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lcd_delay(166670);
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lcd_write_reg(0x11, 0x000C);
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lcd_write_reg(0x12, 0x0A1C);
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lcd_write_reg(0x13, 0x0022);
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lcd_write_reg(0x14, 0x0000);
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lcd_write_reg(0x10, 0x7404);
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lcd_write_reg(0x11, 0x0738);
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lcd_write_reg(0x10, 0x7404);
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lcd_delay(833350);
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|
||||||
lcd_write_reg(0x07, 0x0009);
|
|
||||||
lcd_write_reg(0x12, 0x065C);
|
|
||||||
lcd_delay(3333400);
|
|
||||||
|
|
||||||
lcd_write_reg(0x01, 0xE127);
|
|
||||||
lcd_write_reg(0x02, 0x0300);
|
|
||||||
lcd_write_reg(0x03, 0x1100);
|
|
||||||
lcd_write_reg(0x08, 0x0008);
|
|
||||||
lcd_write_reg(0x0B, 0x0000);
|
|
||||||
lcd_write_reg(0x0C, 0x0000);
|
|
||||||
lcd_write_reg(0x0D, 0x0007);
|
|
||||||
lcd_write_reg(0x15, 0x0003);
|
|
||||||
lcd_write_reg(0x16, 0x0014);
|
|
||||||
lcd_write_reg(0x17, 0x0000);
|
|
||||||
|
|
||||||
lcd_write_reg(0x30, 0x0503); /* gamma? */
|
|
||||||
lcd_write_reg(0x31, 0x0303);
|
|
||||||
lcd_write_reg(0x32, 0x0305);
|
|
||||||
lcd_write_reg(0x33, 0x0202);
|
|
||||||
lcd_write_reg(0x34, 0x0204);
|
|
||||||
lcd_write_reg(0x35, 0x0404);
|
|
||||||
lcd_write_reg(0x36, 0x0402);
|
|
||||||
lcd_write_reg(0x37, 0x0202);
|
|
||||||
lcd_write_reg(0x38, 0x1000);
|
|
||||||
lcd_write_reg(0x39, 0x1000);
|
|
||||||
|
|
||||||
lcd_write_reg(0x07, 0x0009);
|
|
||||||
lcd_delay(666680);
|
|
||||||
|
|
||||||
lcd_write_reg(0x07, 0x0109);
|
|
||||||
lcd_delay(666680);
|
|
||||||
|
|
||||||
lcd_write_reg(0x07, 0x010B);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* lcd enable for lcd type 1 */
|
|
||||||
static void lcd_enable1(bool on)
|
|
||||||
{
|
|
||||||
if (on) {
|
|
||||||
lcd_write_reg(0x00, 0x0001); /* start oscillation */
|
|
||||||
lcd_delay(166670);
|
|
||||||
lcd_write_reg(0x10, 0x0000); /* power control 1 */
|
|
||||||
lcd_delay(166670);
|
|
||||||
|
|
||||||
lcd_write_reg(0x11, 0x3304); /* power control 2 */
|
|
||||||
lcd_write_reg(0x14, 0x1300); /* power control 4 */
|
|
||||||
lcd_write_reg(0x10, 0x1A20); /* power control 1 */
|
|
||||||
lcd_write_reg(0x07, 0x0015); /* display control */
|
|
||||||
lcd_delay(500000);
|
|
||||||
|
|
||||||
lcd_write_reg(0x20, 0x0000); /* RAM address set (low part) */
|
|
||||||
lcd_write_reg(0x21, 0x0000); /* RAM address set (high part) */
|
|
||||||
lcd_write_reg(0x22, 0x0000); /* write data to GRAM */
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
lcd_write_reg(0x07, 0x0016); /* display control */
|
|
||||||
lcd_delay(166670 * 4);
|
|
||||||
lcd_write_reg(0x07, 0x0004); /* display control */
|
|
||||||
lcd_delay(166670 * 4);
|
|
||||||
|
|
||||||
lcd_write_reg(0x10, 0x1E21); /* power control 1 */
|
|
||||||
lcd_delay(166670);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* lcd enable for lcd type 2 */
|
|
||||||
static void lcd_enable2(bool on)
|
|
||||||
{
|
|
||||||
if (on) {
|
|
||||||
lcd_write_reg(0x10, 0x0400);
|
|
||||||
lcd_delay(666680);
|
|
||||||
|
|
||||||
lcd_write_reg(0x07, 0x0000);
|
|
||||||
lcd_write_reg(0x12, 0x0000);
|
|
||||||
lcd_delay(166670);
|
|
||||||
|
|
||||||
lcd_write_reg(0x11, 0x000C);
|
|
||||||
lcd_write_reg(0x12, 0x0A1C);
|
|
||||||
lcd_write_reg(0x13, 0x0022);
|
|
||||||
lcd_write_reg(0x14, 0x0000);
|
|
||||||
lcd_write_reg(0x10, 0x7404);
|
|
||||||
lcd_write_reg(0x11, 0x0738);
|
|
||||||
lcd_write_reg(0x10, 0x7404);
|
|
||||||
lcd_delay(833350);
|
|
||||||
|
|
||||||
lcd_write_reg(0x07, 0x0009);
|
|
||||||
lcd_write_reg(0x12, 0x065C);
|
|
||||||
lcd_delay(3333400);
|
|
||||||
|
|
||||||
lcd_write_reg(0x0B, 0x0000);
|
|
||||||
lcd_write_reg(0x07, 0x0009);
|
|
||||||
lcd_delay(666680);
|
|
||||||
|
|
||||||
lcd_write_reg(0x07, 0x0109);
|
|
||||||
lcd_delay(666680);
|
|
||||||
|
|
||||||
lcd_write_reg(0x07, 0x010B);
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
lcd_write_reg(0x0B, 0x0109);
|
|
||||||
lcd_write_reg(0x07, 0x0009);
|
|
||||||
lcd_delay(666680);
|
|
||||||
|
|
||||||
lcd_write_reg(0x07, 0x0008);
|
|
||||||
lcd_delay(666680);
|
|
||||||
|
|
||||||
lcd_write_reg(0x10, 0x0400);
|
|
||||||
lcd_write_reg(0x10, 0x0401);
|
|
||||||
lcd_delay(166670);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* turn both the lcd controller and the lcd itself on or off */
|
|
||||||
void lcd_enable(bool on)
|
|
||||||
{
|
|
||||||
if (on) {
|
|
||||||
/* enable controller clock */
|
|
||||||
PWRCON &= ~(1 << 18);
|
|
||||||
|
|
||||||
lcd_controller_power(true);
|
|
||||||
lcd_delay(166670);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* call type specific power function */
|
|
||||||
if (lcd_type == 1) {
|
|
||||||
lcd_enable1(on);
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
lcd_enable2(on);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!on) {
|
|
||||||
lcd_controller_power(false);
|
|
||||||
|
|
||||||
/* disable controller clock */
|
|
||||||
PWRCON |= (1 << 18);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* initialise the lcd controller inside the s5l8700 */
|
/* enable/disable clock signals towards the lcd */
|
||||||
static void lcd_controller_init(void)
|
static void lcd_controller_power(bool on)
|
||||||
{
|
{
|
||||||
|
if (on) {
|
||||||
|
LCDCON1 |= 0x80003;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
LCDCON1 &= ~0x80003;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* lcd init configuration for lcd type 1 */
|
||||||
|
static void lcd_init1(void)
|
||||||
|
{
|
||||||
|
lcd_write_reg(0x07, 0x0000); /* display control */
|
||||||
|
lcd_write_reg(0x13, 0x0000); /* power control 3 */
|
||||||
|
lcd_delay(166670);
|
||||||
|
|
||||||
|
lcd_write_reg(0x11, 0x3304); /* power control 2 */
|
||||||
|
lcd_write_reg(0x14, 0x1300); /* power control 4 */
|
||||||
|
lcd_write_reg(0x10, 0x1A20); /* power control 1 */
|
||||||
|
lcd_write_reg(0x13, 0x0040); /* power control 3 */
|
||||||
|
lcd_delay(833350);
|
||||||
|
|
||||||
|
lcd_write_reg(0x13, 0x0060); /* power control 3 */
|
||||||
|
lcd_write_reg(0x13, 0x0070); /* power control 3 */
|
||||||
|
lcd_delay(3333400);
|
||||||
|
|
||||||
|
lcd_write_reg(0x01, 0x0127); /* driver output control */
|
||||||
|
lcd_write_reg(0x02, 0x0700); /* lcd driving waveform control */
|
||||||
|
lcd_write_reg(0x03, 0x1030); /* entry mode */
|
||||||
|
lcd_write_reg(0x08, 0x0208); /* blank period control 1 */
|
||||||
|
lcd_write_reg(0x0B, 0x0620); /* frame cycle control */
|
||||||
|
lcd_write_reg(0x0C, 0x0110); /* external interface control */
|
||||||
|
lcd_write_reg(0x30, 0x0120); /* gamma control 1 */
|
||||||
|
lcd_write_reg(0x31, 0x0117); /* gamma control 2 */
|
||||||
|
lcd_write_reg(0x32, 0x0000); /* gamma control 3 */
|
||||||
|
lcd_write_reg(0x33, 0x0305); /* gamma control 4 */
|
||||||
|
lcd_write_reg(0x34, 0x0717); /* gamma control 5 */
|
||||||
|
lcd_write_reg(0x35, 0x0124); /* gamma control 6 */
|
||||||
|
lcd_write_reg(0x36, 0x0706); /* gamma control 7 */
|
||||||
|
lcd_write_reg(0x37, 0x0503); /* gamma control 8 */
|
||||||
|
lcd_write_reg(0x38, 0x1F03); /* gamma control 9 */
|
||||||
|
lcd_write_reg(0x39, 0x0009); /* gamma control 10 */
|
||||||
|
lcd_write_reg(0x40, 0x0000); /* gate scan position */
|
||||||
|
lcd_write_reg(0x41, 0x0000); /* vertical scroll control */
|
||||||
|
lcd_write_reg(0x42, 0x013F); /* 1st screen driving position (end) */
|
||||||
|
lcd_write_reg(0x43, 0x0000); /* 1st screen driving position (start) */
|
||||||
|
lcd_write_reg(0x44, 0x013F); /* 2nd screen driving position (end) */
|
||||||
|
lcd_write_reg(0x45, 0x0000); /* 2nd screen driving position (start) */
|
||||||
|
lcd_write_reg(0x46, 0xEF00); /* horizontal window address */
|
||||||
|
lcd_write_reg(0x47, 0x013F); /* vertical window address (end) */
|
||||||
|
lcd_write_reg(0x48, 0x0000); /* vertical window address (start) */
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x0015); /* display control */
|
||||||
|
lcd_delay(500000);
|
||||||
|
lcd_write_reg(0x07, 0x0017); /* display control */
|
||||||
|
|
||||||
|
lcd_write_reg(0x20, 0x0000); /* RAM address set (low part) */
|
||||||
|
lcd_write_reg(0x21, 0x0000); /* RAM address set (high part) */
|
||||||
|
lcd_write_reg(0x22, 0x0000); /* write data to GRAM */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* lcd init configuration for lcd type 2 */
|
||||||
|
static void lcd_init2(void)
|
||||||
|
{
|
||||||
|
lcd_write_reg(0x07, 0x0000);
|
||||||
|
lcd_write_reg(0x12, 0x0000);
|
||||||
|
lcd_delay(166670);
|
||||||
|
|
||||||
|
lcd_write_reg(0x11, 0x000C);
|
||||||
|
lcd_write_reg(0x12, 0x0A1C);
|
||||||
|
lcd_write_reg(0x13, 0x0022);
|
||||||
|
lcd_write_reg(0x14, 0x0000);
|
||||||
|
|
||||||
|
lcd_write_reg(0x10, 0x7404);
|
||||||
|
lcd_write_reg(0x11, 0x0738);
|
||||||
|
lcd_write_reg(0x10, 0x7404);
|
||||||
|
lcd_delay(833350);
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x0009);
|
||||||
|
lcd_write_reg(0x12, 0x065C);
|
||||||
|
lcd_delay(3333400);
|
||||||
|
|
||||||
|
lcd_write_reg(0x01, 0xE127);
|
||||||
|
lcd_write_reg(0x02, 0x0300);
|
||||||
|
lcd_write_reg(0x03, 0x1100);
|
||||||
|
lcd_write_reg(0x08, 0x0008);
|
||||||
|
lcd_write_reg(0x0B, 0x0000);
|
||||||
|
lcd_write_reg(0x0C, 0x0000);
|
||||||
|
lcd_write_reg(0x0D, 0x0007);
|
||||||
|
lcd_write_reg(0x15, 0x0003);
|
||||||
|
lcd_write_reg(0x16, 0x0014);
|
||||||
|
lcd_write_reg(0x17, 0x0000);
|
||||||
|
|
||||||
|
lcd_write_reg(0x30, 0x0503); /* gamma? */
|
||||||
|
lcd_write_reg(0x31, 0x0303);
|
||||||
|
lcd_write_reg(0x32, 0x0305);
|
||||||
|
lcd_write_reg(0x33, 0x0202);
|
||||||
|
lcd_write_reg(0x34, 0x0204);
|
||||||
|
lcd_write_reg(0x35, 0x0404);
|
||||||
|
lcd_write_reg(0x36, 0x0402);
|
||||||
|
lcd_write_reg(0x37, 0x0202);
|
||||||
|
lcd_write_reg(0x38, 0x1000);
|
||||||
|
lcd_write_reg(0x39, 0x1000);
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x0009);
|
||||||
|
lcd_delay(666680);
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x0109);
|
||||||
|
lcd_delay(666680);
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x010B);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* lcd enable for lcd type 1 */
|
||||||
|
static void lcd_enable1(bool on)
|
||||||
|
{
|
||||||
|
if (on) {
|
||||||
|
lcd_write_reg(0x00, 0x0001); /* start oscillation */
|
||||||
|
lcd_delay(166670);
|
||||||
|
lcd_write_reg(0x10, 0x0000); /* power control 1 */
|
||||||
|
lcd_delay(166670);
|
||||||
|
|
||||||
|
lcd_write_reg(0x11, 0x3304); /* power control 2 */
|
||||||
|
lcd_write_reg(0x14, 0x1300); /* power control 4 */
|
||||||
|
lcd_write_reg(0x10, 0x1A20); /* power control 1 */
|
||||||
|
lcd_write_reg(0x07, 0x0015); /* display control */
|
||||||
|
lcd_delay(500000);
|
||||||
|
|
||||||
|
lcd_write_reg(0x20, 0x0000); /* RAM address set (low part) */
|
||||||
|
lcd_write_reg(0x21, 0x0000); /* RAM address set (high part) */
|
||||||
|
lcd_write_reg(0x22, 0x0000); /* write data to GRAM */
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
lcd_write_reg(0x07, 0x0016); /* display control */
|
||||||
|
lcd_delay(166670 * 4);
|
||||||
|
lcd_write_reg(0x07, 0x0004); /* display control */
|
||||||
|
lcd_delay(166670 * 4);
|
||||||
|
|
||||||
|
lcd_write_reg(0x10, 0x1E21); /* power control 1 */
|
||||||
|
lcd_delay(166670);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* lcd enable for lcd type 2 */
|
||||||
|
static void lcd_enable2(bool on)
|
||||||
|
{
|
||||||
|
if (on) {
|
||||||
|
lcd_write_reg(0x10, 0x0400);
|
||||||
|
lcd_delay(666680);
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x0000);
|
||||||
|
lcd_write_reg(0x12, 0x0000);
|
||||||
|
lcd_delay(166670);
|
||||||
|
|
||||||
|
lcd_write_reg(0x11, 0x000C);
|
||||||
|
lcd_write_reg(0x12, 0x0A1C);
|
||||||
|
lcd_write_reg(0x13, 0x0022);
|
||||||
|
lcd_write_reg(0x14, 0x0000);
|
||||||
|
lcd_write_reg(0x10, 0x7404);
|
||||||
|
lcd_write_reg(0x11, 0x0738);
|
||||||
|
lcd_write_reg(0x10, 0x7404);
|
||||||
|
lcd_delay(833350);
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x0009);
|
||||||
|
lcd_write_reg(0x12, 0x065C);
|
||||||
|
lcd_delay(3333400);
|
||||||
|
|
||||||
|
lcd_write_reg(0x0B, 0x0000);
|
||||||
|
lcd_write_reg(0x07, 0x0009);
|
||||||
|
lcd_delay(666680);
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x0109);
|
||||||
|
lcd_delay(666680);
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x010B);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
lcd_write_reg(0x0B, 0x0109);
|
||||||
|
lcd_write_reg(0x07, 0x0009);
|
||||||
|
lcd_delay(666680);
|
||||||
|
|
||||||
|
lcd_write_reg(0x07, 0x0008);
|
||||||
|
lcd_delay(666680);
|
||||||
|
|
||||||
|
lcd_write_reg(0x10, 0x0400);
|
||||||
|
lcd_write_reg(0x10, 0x0401);
|
||||||
|
lcd_delay(166670);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* turn both the lcd controller and the lcd itself on or off */
|
||||||
|
void lcd_enable(bool on)
|
||||||
|
{
|
||||||
|
if (on) {
|
||||||
|
/* enable controller clock */
|
||||||
|
PWRCON &= ~(1 << 18);
|
||||||
|
|
||||||
|
lcd_controller_power(true);
|
||||||
|
lcd_delay(166670);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* call type specific power function */
|
||||||
|
if (lcd_type == 1) {
|
||||||
|
lcd_enable1(on);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
lcd_enable2(on);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!on) {
|
||||||
|
lcd_controller_power(false);
|
||||||
|
|
||||||
|
/* disable controller clock */
|
||||||
|
PWRCON |= (1 << 18);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* initialise the lcd controller inside the s5l8700 */
|
||||||
|
static void lcd_controller_init(void)
|
||||||
|
{
|
||||||
PWRCON &= ~(1 << 18);
|
PWRCON &= ~(1 << 18);
|
||||||
|
|
||||||
LCDCON1 = (0 << 28) | /* BURSTLEN */
|
LCDCON1 = (0 << 28) | /* BURSTLEN */
|
||||||
|
|
@ -379,80 +379,80 @@ static void lcd_controller_init(void)
|
||||||
(1 << 3); /* IVDEN */
|
(1 << 3); /* IVDEN */
|
||||||
LCDTCON1 = (lcd_type == 1) ? 0x070103 : 0x030303;
|
LCDTCON1 = (lcd_type == 1) ? 0x070103 : 0x030303;
|
||||||
LCDTCON2 = (lcd_type == 1) ? 0x070103 : 0x030703;
|
LCDTCON2 = (lcd_type == 1) ? 0x070103 : 0x030703;
|
||||||
LCDTCON3 = ((LCD_HEIGHT - 1) << 11) | (LCD_WIDTH - 1);
|
LCDTCON3 = ((LCD_HEIGHT - 1) << 11) | (LCD_WIDTH - 1);
|
||||||
LCDOSD1 = 0;
|
LCDOSD1 = 0;
|
||||||
LCDOSD2 = 0;
|
LCDOSD2 = 0;
|
||||||
LCDOSD3 = 0;
|
LCDOSD3 = 0;
|
||||||
|
|
||||||
LCDB1SADDR1 = 0;
|
LCDB1SADDR1 = 0;
|
||||||
LCDB2SADDR1 = 0;
|
LCDB2SADDR1 = 0;
|
||||||
LCDF1SADDR1 = 0;
|
LCDF1SADDR1 = 0;
|
||||||
LCDF2SADDR1 = 0;
|
LCDF2SADDR1 = 0;
|
||||||
LCDB1SADDR2 = 0;
|
LCDB1SADDR2 = 0;
|
||||||
LCDB2SADDR2 = 0;
|
LCDB2SADDR2 = 0;
|
||||||
LCDF1SADDR2 = 0;
|
LCDF1SADDR2 = 0;
|
||||||
LCDF2SADDR2 = 0;
|
LCDF2SADDR2 = 0;
|
||||||
LCDB1SADDR3 = 0;
|
LCDB1SADDR3 = 0;
|
||||||
LCDB2SADDR3 = 0;
|
LCDB2SADDR3 = 0;
|
||||||
LCDF1SADDR3 = 0;
|
LCDF1SADDR3 = 0;
|
||||||
LCDF2SADDR3 = 0;
|
LCDF2SADDR3 = 0;
|
||||||
|
|
||||||
LCDKEYCON = 0;
|
LCDKEYCON = 0;
|
||||||
LCDCOLVAL = 0;
|
LCDCOLVAL = 0;
|
||||||
LCDBGCON = 0;
|
LCDBGCON = 0;
|
||||||
LCDFGCON = 0;
|
LCDFGCON = 0;
|
||||||
LCDDITHMODE = 0;
|
LCDDITHMODE = 0;
|
||||||
|
|
||||||
LCDINTCON = 0;
|
LCDINTCON = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void lcd_init_device(void)
|
void lcd_init_device(void)
|
||||||
{
|
{
|
||||||
unsigned int lcd_id;
|
unsigned int lcd_id;
|
||||||
uint32_t fb, fb_end, window;
|
uint32_t fb, fb_end, window;
|
||||||
|
|
||||||
/* configure LCD SPI pins */
|
/* configure LCD SPI pins */
|
||||||
lcd_spi_init();
|
lcd_spi_init();
|
||||||
|
|
||||||
/* identify display through SPI */
|
/* identify display through SPI */
|
||||||
lcd_id = lcd_read_reg(0);
|
lcd_id = lcd_read_reg(0);
|
||||||
lcd_type = (lcd_id == LCD_TYPE1_ID) ? 1 : 2;
|
lcd_type = (lcd_id == LCD_TYPE1_ID) ? 1 : 2;
|
||||||
|
|
||||||
/* display specific init sequence */
|
/* display specific init sequence */
|
||||||
if (lcd_type == 1) {
|
if (lcd_type == 1) {
|
||||||
lcd_init1();
|
lcd_init1();
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
lcd_init2();
|
lcd_init2();
|
||||||
}
|
}
|
||||||
|
|
||||||
/* init LCD controller */
|
/* init LCD controller */
|
||||||
lcd_controller_init();
|
lcd_controller_init();
|
||||||
|
|
||||||
/* set framebuffer addresses */
|
/* set framebuffer addresses */
|
||||||
fb = (uint32_t) &lcd_framebuffer[0][0];
|
fb = (uint32_t) &lcd_framebuffer[0][0];
|
||||||
fb_end = (uint32_t) &lcd_framebuffer[LCD_HEIGHT][0];
|
fb_end = (uint32_t) &lcd_framebuffer[LCD_HEIGHT][0];
|
||||||
window = 2 * LCD_WIDTH;
|
window = 2 * LCD_WIDTH;
|
||||||
|
|
||||||
LCDB1SADDR1 = fb;
|
LCDB1SADDR1 = fb;
|
||||||
LCDB2SADDR1 = fb;
|
LCDB2SADDR1 = fb;
|
||||||
LCDF1SADDR1 = fb;
|
LCDF1SADDR1 = fb;
|
||||||
LCDF2SADDR1 = fb;
|
LCDF2SADDR1 = fb;
|
||||||
|
|
||||||
LCDB1SADDR2 = fb_end;
|
LCDB1SADDR2 = fb_end;
|
||||||
LCDB2SADDR2 = fb_end;
|
LCDB2SADDR2 = fb_end;
|
||||||
LCDF1SADDR2 = fb_end;
LCDF2SADDR2 = fb_end;
|
LCDF1SADDR2 = fb_end;
LCDF2SADDR2 = fb_end;
|
||||||
|
|
||||||
LCDB1SADDR3 = window;
|
LCDB1SADDR3 = window;
|
||||||
LCDB2SADDR3 = window;
|
LCDB2SADDR3 = window;
|
||||||
LCDF1SADDR3 = window;
|
LCDF1SADDR3 = window;
|
||||||
LCDF2SADDR3 = window;
|
LCDF2SADDR3 = window;
|
||||||
|
|
||||||
lcd_enable(true);
|
lcd_enable(true);
|
||||||
|
|
||||||
/* configure LCD pins */
|
/* configure LCD pins */
|
||||||
PCON_ASRAM = 1;
|
PCON_ASRAM = 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
void lcd_update_rect(int x, int y, int width, int height)
|
void lcd_update_rect(int x, int y, int width, int height)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
56
firmware/target/arm/s5l8700/meizu-m6sp/nand-target.h
Normal file
56
firmware/target/arm/s5l8700/meizu-m6sp/nand-target.h
Normal file
|
|
@ -0,0 +1,56 @@
|
||||||
|
/***************************************************************************
|
||||||
|
* __________ __ ___.
|
||||||
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||||
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||||
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||||
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||||
|
* \/ \/ \/ \/ \/
|
||||||
|
* $Id$
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009 by Michael Sparmann
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* as published by the Free Software Foundation; either version 2
|
||||||
|
* of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||||
|
* KIND, either express or implied.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __NAND_TARGET_H__
|
||||||
|
#define __NAND_TARGET_H__
|
||||||
|
|
||||||
|
#include "config.h"
|
||||||
|
#include "inttypes.h"
|
||||||
|
|
||||||
|
|
||||||
|
struct nand_device_info_type
|
||||||
|
{
|
||||||
|
uint32_t id;
|
||||||
|
uint16_t blocks;
|
||||||
|
uint16_t userblocks;
|
||||||
|
uint16_t pagesperblock;
|
||||||
|
uint8_t blocksizeexponent;
|
||||||
|
uint8_t tunk1;
|
||||||
|
uint8_t twp;
|
||||||
|
uint8_t tunk2;
|
||||||
|
uint8_t tunk3;
|
||||||
|
} __attribute__((packed));
|
||||||
|
|
||||||
|
uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
|
||||||
|
void* sparebuffer, uint32_t doecc,
|
||||||
|
uint32_t checkempty);
|
||||||
|
uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
|
||||||
|
void* sparebuffer, uint32_t doecc);
|
||||||
|
uint32_t nand_block_erase(uint32_t bank, uint32_t page);
|
||||||
|
|
||||||
|
const struct nand_device_info_type* nand_get_device_type(uint32_t bank);
|
||||||
|
uint32_t nand_reset(uint32_t bank);
|
||||||
|
uint32_t nand_device_init(void);
|
||||||
|
void nand_power_up(void);
|
||||||
|
void nand_power_down(void);
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Add table
Add a link
Reference in a new issue