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arm: implement cache maintenance ops for ARMv7-M

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To keep the code size small, this hardcodes the D-Cache line
size and set/way information (which is defined by the target
and should be fixed for a given CPU) and assumes there is only
one level of cache.

Change-Id: Ia6d0e6a87b5dbfc6c39bda83b58461ed8767edf6
This commit is contained in:
Aidan MacDonald 2025-01-09 07:36:59 +00:00 • committed by Solomon Peachy
parent 4d3190f416
commit d14ddcafd5
3 changed files with 148 additions and 0 deletions
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firmware/SOURCES
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@ -608,6 +608,8 @@ target/arm/mmu-arm.S
# elif ARM_ARCH == 6
target/arm/bits-armv6.S
target/arm/mmu-armv6.S
# elif ARM_ARCH == 7 && ARM_PROFILE == ARM_PROFILE_MICRO
target/arm/cpucache-armv7m.c
# endif
#if defined(CPU_ARM_CLASSIC)