mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-11-09 13:12:37 -05:00
iPod Nano 2G USB support based on the S3C6400X datasheet. Disabled by default for now.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23285 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann
parent
3ad3bec0ad
commit
d03fe64dcf
7 changed files with 790 additions and 60 deletions
429
firmware/target/arm/usb-s3c6400x.c
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429
firmware/target/arm/usb-s3c6400x.c
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "usb.h"
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#define OTGBASE 0x38800000
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#define PHYBASE 0x3C400000
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#include "usb-s3c6400x.h"
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#include "cpu.h"
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#include "system.h"
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#include "kernel.h"
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#include "panic.h"
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#ifdef HAVE_USBSTACK
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#include "usb_ch9.h"
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#include "usb_core.h"
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#include <inttypes.h>
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#include "sprintf.h"
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#include "power.h"
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struct ep_type
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{
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bool active;
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bool busy;
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bool done;
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int rc;
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int size;
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struct wakeup complete;
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} ;
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static struct ep_type endpoints[5];
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static struct usb_ctrlrequest ctrlreq USB_DEVBSS_ATTR;
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int usb_drv_port_speed(void)
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{
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return (DSTS & 2) == 0 ? 1 : 0;
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}
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void reset_endpoints(int reinit)
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{
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unsigned int i;
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for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
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{
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if (reinit) endpoints[i].active = false;
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endpoints[i].busy = false;
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endpoints[i].rc = -1;
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endpoints[i].done = true;
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wakeup_signal(&endpoints[i].complete);
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}
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DIEPCTL0 = 0x8800; /* EP0 IN ACTIVE NEXT=1 */
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DOEPCTL0 = 0x8000; /* EP0 OUT ACTIVE */
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DOEPTSIZ0 = 0x20080040; /* EP0 OUT Transfer Size:
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64 Bytes, 1 Packet, 1 Setup Packet */
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DOEPDMA0 = (uint32_t)&ctrlreq;
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DOEPCTL0 |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */
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if (reinit)
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{
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/* The size is getting set to zero, because we don't know
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whether we are Full Speed or High Speed at this stage */
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/* EP1 IN INACTIVE DATA0 SIZE=0 NEXT=3 */
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DIEPCTL1 = 0x10001800;
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/* EP2 OUT INACTIVE DATA0 SIZE=0 */
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DOEPCTL2 = 0x10000000;
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/* EP3 IN INACTIVE DATA0 SIZE=0 NEXT=0 */
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DIEPCTL3 = 0x10000000;
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/* EP4 OUT INACTIVE DATA0 SIZE=0 */
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DOEPCTL4 = 0x10000000;
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}
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else
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{
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/* INACTIVE DATA0 */
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DIEPCTL1 = (DIEPCTL1 & ~0x00008000) | 0x10000000;
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DOEPCTL2 = (DOEPCTL2 & ~0x00008000) | 0x10000000;
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DIEPCTL3 = (DIEPCTL3 & ~0x00008000) | 0x10000000;
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DOEPCTL4 = (DOEPCTL4 & ~0x00008000) | 0x10000000;
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}
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DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all EPs */
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}
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int usb_drv_request_endpoint(int type, int dir)
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{
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size_t ep;
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int ret = -1;
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if (dir == USB_DIR_IN) ep = 1;
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else ep = 2;
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while (ep < 5)
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{
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if (!endpoints[ep].active)
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{
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endpoints[ep].active = true;
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ret = ep | dir;
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uint32_t newbits = (type << 18) | 0x10000000;
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if (dir) DIEPCTL(ep) = (DIEPCTL(ep) & ~0x000C0000) | newbits;
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else DOEPCTL(ep) = (DOEPCTL(ep) & ~0x000C0000) | newbits;
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break;
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}
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ep += 2;
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}
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return ret;
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}
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void usb_drv_release_endpoint(int ep)
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{
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ep = ep & 0x7f;
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if (ep < 1 || ep > USB_NUM_ENDPOINTS) return;
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endpoints[ep].active = false;
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}
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static void usb_reset(void)
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{
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volatile int i;
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DCTL = 0x802; /* Soft Disconnect */
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OPHYPWR = 0; /* PHY: Power up */
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ORSTCON = 1; /* PHY: Assert Software Reset */
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for (i = 0; i < 50; i++);
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ORSTCON = 0; /* PHY: Deassert Software Reset */
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OPHYCLK = 0; /* PHY: 48MHz clock */
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GRSTCTL = 1; /* OTG: Assert Software Reset */
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while (GRSTCTL & 1); /* Wait for OTG to ack reset */
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while (!(GRSTCTL & 0x80000000)); /* Wait for OTG AHB master idle */
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GAHBCFG = 0x27; /* OTG AHB config: Unmask ints, burst length 4, DMA on */
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GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */
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DCFG = 4; /* Address 0 */
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DCTL = 0x800; /* Soft Reconnect */
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DIEPMSK = 0x0D; /* IN EP interrupt mask */
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DOEPMSK = 0x0D; /* IN EP interrupt mask */
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GINTMSK = 0xC3000; /* Interrupt mask: IN event, OUT event, bus reset */
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reset_endpoints(1);
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}
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/* IRQ handler */
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void INT_USB_FUNC(void)
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{
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int i;
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if (GINTSTS & 0x1000) /* bus reset */
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{
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DCFG = 4; /* Address 0 */
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reset_endpoints(1);
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usb_core_bus_reset();
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}
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if (GINTSTS & 0x2000) /* enumeration done, we now know the speed */
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{
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/* Set up the maximum packet sizes accordingly */
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uint32_t maxpacket = usb_drv_port_speed() ? 512 : 64;
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DIEPCTL1 = (DIEPCTL1 & ~0x000003FF) | maxpacket;
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DOEPCTL2 = (DOEPCTL2 & ~0x000003FF) | maxpacket;
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DIEPCTL3 = (DIEPCTL3 & ~0x000003FF) | maxpacket;
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DOEPCTL4 = (DOEPCTL4 & ~0x000003FF) | maxpacket;
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}
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if (GINTSTS & 0x40000) /* IN EP event */
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for (i = 0; i < 5; i ++)
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if (i != 2 && i != 4 && DIEPINT(i))
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{
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if (DIEPINT(i) & 1) /* Transfer completed */
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{
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invalidate_dcache();
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int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF);
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if (endpoints[i].busy)
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{
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endpoints[i].busy = false;
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endpoints[i].rc = 0;
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endpoints[i].done = true;
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usb_core_transfer_complete(i, USB_DIR_IN, 0, bytes);
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wakeup_signal(&endpoints[i].complete);
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}
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}
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if (DIEPINT(i) & 4) /* AHB error */
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panicf("USB: AHB error on IN EP%d", i);
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if (DIEPINT(i) & 8) /* Timeout */
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{
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if (endpoints[i].busy)
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{
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endpoints[i].busy = false;
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endpoints[i].rc = 1;
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endpoints[i].done = true;
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wakeup_signal(&endpoints[i].complete);
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}
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}
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DIEPINT(i) = DIEPINT(i);
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}
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if (GINTSTS & 0x80000) /* OUT EP event */
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for (i = 0; i < 5; i += 2)
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if (DOEPINT(i))
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{
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if (DOEPINT(i) & 1) /* Transfer completed */
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{
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invalidate_dcache();
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int bytes = endpoints[i].size - (DOEPTSIZ(i) & 0x3FFFF);
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if (endpoints[i].busy)
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{
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endpoints[i].busy = false;
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endpoints[i].rc = 0;
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endpoints[i].done = true;
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usb_core_transfer_complete(i, USB_DIR_OUT, 0, bytes);
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wakeup_signal(&endpoints[i].complete);
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}
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}
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if (DOEPINT(i) & 4) /* AHB error */
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panicf("USB: AHB error on OUT EP%d", i);
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if (DOEPINT(i) & 8) /* SETUP phase done */
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{
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invalidate_dcache();
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if (i == 0)
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{
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if (ctrlreq.bRequest == 5)
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{
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/* Already set the new address here,
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before passing the packet to the core.
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See below (usb_drv_set_address) for details. */
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DCFG = (DCFG & ~0x7F0) | (ctrlreq.wValue << 4);
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}
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usb_core_control_request(&ctrlreq);
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}
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else panicf("USB: SETUP done on OUT EP%d!?", i);
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}
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/* Make sure EP0 OUT is set up to accept the next request */
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if (!i)
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{
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DOEPTSIZ0 = 0x20080040;
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DOEPDMA0 = (uint32_t)&ctrlreq;
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DOEPCTL0 |= 0x84000000;
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}
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DOEPINT(i) = DOEPINT(i);
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}
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GINTSTS = GINTSTS;
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}
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void usb_drv_set_address(int address)
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{
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(void)address;
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/* Ignored intentionally, because the controller requires us to set the
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new address before sending the response for some reason. So we'll
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already set it when the control request arrives, before passing that
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into the USB core, which will then call this dummy function. */
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}
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void ep_send(int ep, void *ptr, int length)
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{
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endpoints[ep].busy = true;
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endpoints[ep].size = length;
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DIEPCTL(ep) |= 0x8000; /* EPx OUT ACTIVE */
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int blocksize = usb_drv_port_speed() ? 512 : 64;
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int packets = (length + blocksize - 1) / blocksize;
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if (!length) DIEPTSIZ(ep) = 1 << 19; /* one empty packet */
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else DIEPTSIZ(ep) = length | (packets << 19);
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DIEPDMA(ep) = (uint32_t)ptr;
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clean_dcache();
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DIEPCTL(ep) |= 0x84000000; /* EPx OUT ENABLE CLEARNAK */
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}
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void ep_recv(int ep, void *ptr, int length)
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{
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endpoints[ep].busy = true;
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endpoints[ep].size = length;
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DOEPCTL(ep) &= ~0x20000; /* EPx UNSTALL */
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DOEPCTL(ep) |= 0x8000; /* EPx OUT ACTIVE */
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int blocksize = usb_drv_port_speed() ? 512 : 64;
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int packets = (length + blocksize - 1) / blocksize;
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if (!length) DIEPTSIZ(ep) = 1 << 19; /* one empty packet */
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else DOEPTSIZ(ep) = length | (packets << 19);
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DOEPDMA(ep) = (uint32_t)ptr;
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clean_dcache();
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DOEPCTL(ep) |= 0x84000000; /* EPx OUT ENABLE CLEARNAK */
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}
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int usb_drv_send(int endpoint, void *ptr, int length)
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{
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endpoint &= 0x7f;
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endpoints[endpoint].done = false;
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ep_send(endpoint, ptr, length);
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while (!endpoints[endpoint].done && endpoints[endpoint].busy)
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wakeup_wait(&endpoints[endpoint].complete, TIMEOUT_BLOCK);
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return endpoints[endpoint].rc;
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}
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int usb_drv_send_nonblocking(int endpoint, void *ptr, int length)
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{
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ep_send(endpoint & 0x7f, ptr, length);
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return 0;
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}
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int usb_drv_recv(int endpoint, void* ptr, int length)
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{
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ep_recv(endpoint & 0x7f, ptr, length);
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return 0;
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}
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void usb_drv_cancel_all_transfers(void)
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{
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int flags = disable_irq_save();
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reset_endpoints(0);
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restore_irq(flags);
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}
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void usb_drv_set_test_mode(int mode)
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{
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(void)mode;
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}
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bool usb_drv_stalled(int endpoint, bool in)
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{
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if (in) return DIEPCTL(endpoint) & 0x00200000 ? true : false;
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else return DOEPCTL(endpoint) & 0x00200000 ? true : false;
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}
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void usb_drv_stall(int endpoint, bool stall, bool in)
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{
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if (in)
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{
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if (stall) DIEPCTL(endpoint) |= 0x00200000;
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else DIEPCTL(endpoint) &= ~0x00200000;
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}
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else
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{
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if (stall) DOEPCTL(endpoint) |= 0x00200000;
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else DOEPCTL(endpoint) &= ~0x00200000;
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}
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}
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void usb_drv_init(void)
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{
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/* Enable USB clock */
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PWRCON &= ~0x4000;
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PWRCONEXT &= ~0x800;
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PCGCCTL = 0;
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/* unmask irq */
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INTMSK |= INTMSK_USB_OTG;
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/* reset the beast */
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usb_reset();
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}
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void usb_drv_exit(void)
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{
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DCTL = 0x802; /* Soft Disconnect */
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OPHYPWR = 0xF; /* PHY: Power down */
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PCGCCTL = 1; /* Mask clocks */
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PWRCON |= 0x4000;
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PWRCONEXT |= 0x800;
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}
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void usb_init_device(void)
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{
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unsigned int i;
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for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
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wakeup_init(&endpoints[i].complete);
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usb_drv_exit();
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}
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void usb_enable(bool on)
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{
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if (on) usb_core_init();
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else usb_core_exit();
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}
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void usb_attach(void)
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{
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usb_enable(true);
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}
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int usb_detect(void)
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{
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if (charger_inserted())
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return USB_INSERTED;
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return USB_EXTRACTED;
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}
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#else
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void usb_init_device(void)
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{
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/* simply switch USB off for now */
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DCTL = 0x802; /* Soft Disconnect */
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OPHYPWR = 0xF; /* PHY: Power down */
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PCGCCTL = 1; /* Mask clocks */
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PWRCON |= 0x4000;
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PWRCONEXT |= 0x800;
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}
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void usb_enable(bool on)
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{
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(void)on;
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}
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/* Always return false for now */
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int usb_detect(void)
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{
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return USB_EXTRACTED;
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}
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#endif
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