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mips: Convert 'nop' to 'ssnop' -- for future-proofing

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Change-Id: I17625f4d56a1f5205887cb47668a2dcb628053f4
This commit is contained in:
Solomon Peachy 2020-09-04 23:50:38 -04:00
parent 8188588f14
commit d015165bc5
6 changed files with 77 additions and 77 deletions
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72
firmware/target/mips/ingenic_jz47xx/crt0.S
View file

@ -108,7 +108,7 @@ _cache_loop:
cache 0x9, 0(t0) # index store dcache tag cache 0x9, 0(t0) # index store dcache tag
addiu t0, t0, 0x20 # 32 bytes per cache line addiu t0, t0, 0x20 # 32 bytes per cache line
bne t0, t1, _cache_loop bne t0, t1, _cache_loop
nop ssnop
/* /*
---------------------------------------------------- ----------------------------------------------------
@ -116,10 +116,10 @@ _cache_loop:
---------------------------------------------------- ----------------------------------------------------
*/ */
mfc0 t0, C0_CONFIG mfc0 t0, C0_CONFIG
nop ssnop
ori t0, 2 ori t0, 2
mtc0 t0, C0_CONFIG mtc0 t0, C0_CONFIG
nop ssnop
/* /*
---------------------------------------------------- ----------------------------------------------------
@ -183,9 +183,9 @@ _irq_stack_loop:
---------------------------------------------------- ----------------------------------------------------
*/ */
jal system_main /* Init clocks etc first */ jal system_main /* Init clocks etc first */
nop ssnop
j main j main
nop ssnop
/* /*
@ -197,19 +197,19 @@ _irq_stack_loop:
.section .vectors.1, "ax", %progbits .section .vectors.1, "ax", %progbits
j tlb_refill_handler j tlb_refill_handler
nop ssnop
.section .vectors.2, "ax", %progbits .section .vectors.2, "ax", %progbits
j real_exception_handler j real_exception_handler
nop ssnop
.section .vectors.3, "ax", %progbits .section .vectors.3, "ax", %progbits
j real_exception_handler j real_exception_handler
nop ssnop
.section .vectors.4, "ax", %progbits .section .vectors.4, "ax", %progbits
j real_exception_handler j real_exception_handler
nop ssnop
.section .vectors, "ax", %progbits .section .vectors, "ax", %progbits
real_exception_handler: real_exception_handler:
@ -253,47 +253,47 @@ real_exception_handler:
sw v0, 0x68(sp) sw v0, 0x68(sp)
sw $1, 0x6C(sp) sw $1, 0x6C(sp)
mflo k0 mflo k0
nop ssnop
sw k0, 0x70(sp) sw k0, 0x70(sp)
mfhi k0 mfhi k0
nop ssnop
sw k0, 0x74(sp) sw k0, 0x74(sp)
mfc0 k0, C0_STATUS mfc0 k0, C0_STATUS
nop ssnop
nop ssnop
nop ssnop
sw k0, 0x78(sp) sw k0, 0x78(sp)
mfc0 k0, C0_EPC mfc0 k0, C0_EPC
nop ssnop
nop ssnop
nop ssnop
sw k0, 0x7C(sp) sw k0, 0x7C(sp)
li k1, M_CauseExcCode li k1, M_CauseExcCode
mfc0 k0, C0_CAUSE mfc0 k0, C0_CAUSE
and k0, k1 and k0, k1
beq zero, k0, _int beq zero, k0, _int
nop ssnop
j _exception j _exception
nop ssnop
_int: _int:
jal intr_handler jal intr_handler
nop ssnop
j _exception_return j _exception_return
_exception: _exception:
move a0, sp move a0, sp
mfc0 a1, C0_CAUSE mfc0 a1, C0_CAUSE
nop ssnop
nop ssnop
nop ssnop
mfc0 a2, C0_EPC mfc0 a2, C0_EPC
nop ssnop
nop ssnop
nop ssnop
jal exception_handler jal exception_handler
nop ssnop
_exception_return: _exception_return:
lw ra, 0(sp) lw ra, 0(sp)
@ -326,23 +326,23 @@ _exception_return:
lw $1, 0x6C(sp) lw $1, 0x6C(sp)
lw k0, 0x70(sp) lw k0, 0x70(sp)
mtlo k0 mtlo k0
nop ssnop
lw k0, 0x74(sp) lw k0, 0x74(sp)
mthi k0 mthi k0
nop ssnop
lw k0, 0x78(sp) lw k0, 0x78(sp)
mtc0 k0, C0_STATUS mtc0 k0, C0_STATUS
nop ssnop
nop ssnop
nop ssnop
lw k0, 0x7C(sp) lw k0, 0x7C(sp)
mtc0 k0, C0_EPC mtc0 k0, C0_EPC
nop ssnop
nop ssnop
nop ssnop
/* Restore previous stack pointer */ /* Restore previous stack pointer */
lw sp, 0x80(sp) lw sp, 0x80(sp)
eret eret
nop ssnop
.set reorder .set reorder
.set at .set at

2
firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
View file

@ -36,7 +36,7 @@ do { \
REG_GPIO_PXPES(2) = 0x001cffff; \ REG_GPIO_PXPES(2) = 0x001cffff; \
} while (0) } while (0)
#define SLEEP(x) { register int __i; for(__i=0; __i<x; __i++) asm volatile("nop\n nop\n"); } #define SLEEP(x) { register int __i; for(__i=0; __i<x; __i++) asm volatile("ssnop\n ssnop\n"); }
#define DELAY SLEEP(700000); #define DELAY SLEEP(700000);
#if ((defined(ONDA_VX777) || defined(ONDA_VX747P)) && !defined(BOOTLOADER)) \ #if ((defined(ONDA_VX777) || defined(ONDA_VX747P)) && !defined(BOOTLOADER)) \

2
firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c
View file

@ -37,7 +37,7 @@ do { \
} while (0) } while (0)
#define SLEEP(x) for(i=0; i<x; i++) asm volatile("nop\n nop\n"); #define SLEEP(x) for(i=0; i<x; i++) asm volatile("ssnop\n ssnop\n");
#define DELAY SLEEP(700000); #define DELAY SLEEP(700000);
static void _display_pin_init(void) static void _display_pin_init(void)
{ {

2
firmware/target/mips/ingenic_jz47xx/system-jz4740.c
View file

@ -550,7 +550,7 @@ void system_exception_wait(void)
{ {
if( (~REG_GPIO_PXPIN(3)) & (1 << 29) ) if( (~REG_GPIO_PXPIN(3)) & (1 << 29) )
return; return;
asm volatile("nop"); asm volatile("ssnop");
} }
} }

2
firmware/target/mips/ingenic_jz47xx/system-jz4760.c
View file

@ -737,7 +737,7 @@ void system_exception_wait(void)
{ {
if( (~REG_GPIO_PXPIN(0)) & (1 << 30) ) if( (~REG_GPIO_PXPIN(0)) & (1 << 30) )
return; return;
asm volatile("nop"); asm volatile("ssnop");
} }
} }

28
firmware/target/mips/mmu-mips.c
View file

@ -36,12 +36,12 @@
__asm__ __volatile__( \ __asm__ __volatile__( \
" .set push \n" \ " .set push \n" \
" .set noreorder \n" \ " .set noreorder \n" \
" nop \n" \ " ssnop \n" \
" nop \n" \ " ssnop \n" \
" nop \n" \ " ssnop \n" \
" nop \n" \ " ssnop \n" \
" nop \n" \ " ssnop \n" \
" nop \n" \ " ssnop \n" \
" .set pop \n"); " .set pop \n");
#define DEFAULT_PAGE_SHIFT PL_4K #define DEFAULT_PAGE_SHIFT PL_4K
@ -137,16 +137,16 @@ void mmu_init(void)
#if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
#define INVALIDATE_BTB() \ #define INVALIDATE_BTB() \
do { \ do { \
unsigned long tmp; \ register unsigned long tmp; \
__asm__ __volatile__( \ __asm__ __volatile__( \
" .set push \n" \ " .set push \n" \
" .set noreorder \n" \ " .set noreorder \n" \
" .set mips32 \n" \ " .set mips32 \n" \
" mfc0 %0, $16, 7 \n" \ " mfc0 %0, $16, 7 \n" \
" nop \n" \ " ssnop \n" \
" ori %0, 2 \n" \ " ori %0, 2 \n" \
" mtc0 %0, $16, 7 \n" \ " mtc0 %0, $16, 7 \n" \
" nop \n" \ " ssnop \n" \
" .set pop \n" \ " .set pop \n" \
: "=&r"(tmp)); \ : "=&r"(tmp)); \
} while (0) } while (0)
@ -178,7 +178,7 @@ void commit_dcache(void) __attribute__((alias("commit_discard_dcache")));
/* Writeback whole D-cache and invalidate D-cache lines */ /* Writeback whole D-cache and invalidate D-cache lines */
void commit_discard_dcache(void) void commit_discard_dcache(void)
{ {
unsigned int i; register unsigned int i;
/* Use index type operation and iterate whole cache */ /* Use index type operation and iterate whole cache */
for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE) for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE)
@ -192,7 +192,7 @@ void commit_discard_dcache(void)
*/ */
void commit_discard_dcache_range(const void *base, unsigned int size) void commit_discard_dcache_range(const void *base, unsigned int size)
{ {
char *s; register char *s;
for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
__CACHE_OP(DCHitWBInv, s); __CACHE_OP(DCHitWBInv, s);
@ -204,7 +204,7 @@ void commit_discard_dcache_range(const void *base, unsigned int size)
*/ */
void commit_dcache_range(const void *base, unsigned int size) void commit_dcache_range(const void *base, unsigned int size)
{ {
char *s; register char *s;
for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE) for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
__CACHE_OP(DCHitWB, s); __CACHE_OP(DCHitWB, s);
@ -217,7 +217,7 @@ void commit_dcache_range(const void *base, unsigned int size)
*/ */
void discard_dcache_range(const void *base, unsigned int size) void discard_dcache_range(const void *base, unsigned int size)
{ {
char *s; register char *s;
if (((int)base & CACHEALIGN_SIZE - 1) || if (((int)base & CACHEALIGN_SIZE - 1) ||
(((int)base + size) & CACHEALIGN_SIZE - 1)) { (((int)base + size) & CACHEALIGN_SIZE - 1)) {
@ -235,7 +235,7 @@ void discard_dcache_range(const void *base, unsigned int size)
/* Invalidate whole I-cache */ /* Invalidate whole I-cache */
static void discard_icache(void) static void discard_icache(void)
{ {
unsigned int i; register unsigned int i;
asm volatile (".set push \n" asm volatile (".set push \n"
".set noreorder \n" ".set noreorder \n"