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Fundamentally rewrite much of the audio DSP.
Creates a standard buffer passing, local data passing and messaging system for processing stages. Stages can be moved to their own source files to reduce clutter and ease assimilation of new ones. dsp.c becomes dsp_core.c which supports an engine and framework for effects. Formats and change notifications are passed along with the buffer so that they arrive at the correct time at each stage in the chain regardless of the internal delays of a particular one. Removes restrictions on the number of samples that can be processed at a time and it pays attention to destination buffer size restrictions without having to limit input count, which also allows pcmbuf to remain fuller and safely set its own buffer limits as it sees fit. There is no longer a need to query input/output counts given a certain number of input samples; just give it the sizes of the source and destination buffers. Works in harmony with stages that are not deterministic in terms of sample input/output ratio (like both resamplers but most notably the timestretch). As a result it fixes quirks with timestretch hanging up with certain settings and it now operates properly throughout its full settings range. Change-Id: Ib206ec78f6f6c79259c5af9009fe021d68be9734 Reviewed-on: http://gerrit.rockbox.org/200 Reviewed-by: Michael Sevakis <jethead71@rockbox.org> Tested-by: Michael Sevakis <jethead71@rockbox.org>
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56 changed files with 4823 additions and 2998 deletions
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@ -300,6 +300,12 @@ static inline uint32_t swaw32_hw(uint32_t value)
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#define BIT_N(n) (1U << (n))
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#endif
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#ifndef MASK_N
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/* Make a mask of n contiguous bits, shifted left by 'shift' */
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#define MASK_N(type, n, shift) \
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((type)((((type)1 << (n)) - (type)1) << (shift)))
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#endif
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/* Declare this as HIGHEST_IRQ_LEVEL if they don't differ */
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#ifndef DISABLE_INTERRUPTS
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#define DISABLE_INTERRUPTS HIGHEST_IRQ_LEVEL
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@ -352,7 +358,7 @@ static inline uint32_t swaw32_hw(uint32_t value)
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/* Define MEM_ALIGN_ATTR which may be used to align e.g. buffers for faster
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* access. */
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#if defined(CPU_ARM)
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#if defined(CPU_ARM)
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/* Use ARMs cache alignment. */
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#define MEM_ALIGN_ATTR CACHEALIGN_ATTR
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#define MEM_ALIGN_SIZE CACHEALIGN_SIZE
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@ -361,12 +367,16 @@ static inline uint32_t swaw32_hw(uint32_t value)
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#define MEM_ALIGN_ATTR __attribute__((aligned(16)))
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#define MEM_ALIGN_SIZE 16
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#else
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/* Do nothing. */
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#define MEM_ALIGN_ATTR
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/* Align pointer size */
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#define MEM_ALIGN_ATTR __attribute__((aligned(sizeof(intptr_t))))
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#define MEM_ALIGN_SIZE sizeof(intptr_t)
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#endif
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#define MEM_ALIGN_UP(x) \
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((typeof (x))ALIGN_UP((uintptr_t)(x), MEM_ALIGN_SIZE))
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#define MEM_ALIGN_DOWN(x) \
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((typeof (x))ALIGN_DOWN((uintptr_t)(x), MEM_ALIGN_SIZE))
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#ifdef STORAGE_WANTS_ALIGN
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#define STORAGE_ALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE)))
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#define STORAGE_ALIGN_DOWN(x) \
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