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imx233: implement basic frequency scaling and enable auto-slow
This does not scale the EMI frequency and keep the processor betweel 261MHz and 454MHz. It can still be improve. The auto-slow divisor could still be change, 8 seems reasonable for now Change-Id: I639bb3f6b7f8efedc7dc58d08127849156eeb1b6
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parent
6c2190ea04
commit
c9ad8688f1
2 changed files with 48 additions and 12 deletions
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@ -35,6 +35,8 @@
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#include "icoll-imx233.h"
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#include "icoll-imx233.h"
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#include "lradc-imx233.h"
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#include "lradc-imx233.h"
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#include "rtc-imx233.h"
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#include "rtc-imx233.h"
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#include "power-imx233.h"
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#include "emi-imx233.h"
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#include "lcd.h"
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#include "lcd.h"
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#include "backlight-target.h"
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#include "backlight-target.h"
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#include "button.h"
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#include "button.h"
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@ -115,6 +117,14 @@ void system_init(void)
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defined(CREATIVE_ZENXFI3) || defined(CREATIVE_ZENXFI2))
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defined(CREATIVE_ZENXFI3) || defined(CREATIVE_ZENXFI2))
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fmradio_i2c_init();
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fmradio_i2c_init();
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#endif
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#endif
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imx233_clkctrl_enable_auto_slow_monitor(AS_CPU_INSTR, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_CPU_DATA, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_TRAFFIC, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_TRAFFIC_JAM, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_APBXDMA, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_APBHDMA, true);
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imx233_clkctrl_set_auto_slow_divisor(AS_DIV_8);
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imx233_clkctrl_enable_auto_slow(true);
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}
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}
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bool imx233_us_elapsed(uint32_t ref, unsigned us_delay)
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bool imx233_us_elapsed(uint32_t ref, unsigned us_delay)
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@ -151,18 +161,44 @@ void set_cpu_frequency(long frequency)
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{
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{
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switch(frequency)
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switch(frequency)
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{
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{
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#if 0
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case IMX233_CPUFREQ_454_MHz:
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case IMX233_CPUFREQ_454_MHz:
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/* clk_h@clk_p/3 */
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/* go back to a known state: everything at 24MHz ! */
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imx233_set_clock_divisor(CLK_AHB, 3);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, true);
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/* clk_p@ref_cpu/1*18/19 */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 1);
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imx233_set_fractional_divisor(CLK_CPU, 19);
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_logf("set freq 454MHz");
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imx233_set_clock_divisor(CLK_CPU, 1);
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/* set VDDD to 1.550 mV (brownout at 1.450 mV) */
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imx233_power_set_regulator(REGULATOR_VDDD, 1550, 1450);
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/* clk_h@clk_p/2 */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 3);
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/* clk_p@ref_cpu/1*18/33 */
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, 19);
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imx233_clkctrl_set_clock_divisor(CLK_CPU, 1);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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/* ref_cpu@480 MHz
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/* ref_cpu@480 MHz
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* clk_p@454.74 MHz
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* ref_emi@480 MHz
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* clk_h@151.58 MHz */
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* clk_emi@130.91 MHz
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* clk_p@261.82 MHz
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* clk_h@130.91 MHz */
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break;
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case IMX233_CPUFREQ_261_MHz:
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/* go back to a known state: everything at 24MHz ! */
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imx233_clkctrl_set_bypass_pll(CLK_CPU, true);
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 1);
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_logf("set freq 261MHz");
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/* set VDDD to 1.550 mV (brownout at 1.275 mV) */
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imx233_power_set_regulator(REGULATOR_VDDD, 1275, 1175);
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/* clk_h@clk_p/2 */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 2);
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/* clk_p@ref_cpu/1*18/33 */
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, 33);
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imx233_clkctrl_set_clock_divisor(CLK_CPU, 1);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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/* ref_cpu@480 MHz
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* ref_emi@480 MHz
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* clk_emi@130.91 MHz
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* clk_p@261.82 MHz
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* clk_h@130.91 MHz */
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break;
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break;
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#endif
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default:
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default:
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break;
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break;
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}
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}
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@ -55,10 +55,10 @@
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#define IMX233_CPUFREQ_64_MHz 64000000
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#define IMX233_CPUFREQ_64_MHz 64000000
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#define IMX233_CPUFREQ_24_MHz 24000000
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#define IMX233_CPUFREQ_24_MHz 24000000
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#define CPUFREQ_DEFAULT IMX233_CPUFREQ_454_MHz
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#define CPUFREQ_DEFAULT IMX233_CPUFREQ_261_MHz
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#define CPUFREQ_NORMAL IMX233_CPUFREQ_454_MHz
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#define CPUFREQ_NORMAL IMX233_CPUFREQ_261_MHz
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#define CPUFREQ_MAX IMX233_CPUFREQ_454_MHz
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#define CPUFREQ_MAX IMX233_CPUFREQ_454_MHz
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#define CPUFREQ_SLEEP IMX233_CPUFREQ_454_MHz
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#define CPUFREQ_SLEEP IMX233_CPUFREQ_261_MHz
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void udelay(unsigned us);
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void udelay(unsigned us);
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bool imx233_us_elapsed(uint32_t ref, unsigned us_delay);
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bool imx233_us_elapsed(uint32_t ref, unsigned us_delay);
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