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The S5L8701 has the LCD controller in a different place.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21896 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Dave Chapman 2009-07-16 00:12:46 +00:00
parent 02f5a001fe
commit c969047fea
1 changed files with 17 additions and 11 deletions
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28
firmware/export/s5l8700.h
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@ -493,17 +493,23 @@
#define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */
/* 26. LCD INTERFACE CONTROLLER */
#define LCD_CON (*(REG32_PTR_T)(0x3C100000)) /* Control register. */
#define LCD_WCMD (*(REG32_PTR_T)(0x3C100004)) /* Write command register. */
#define LCD_RCMD (*(REG32_PTR_T)(0x3C10000C)) /* Read command register. */
#define LCD_RDATA (*(REG32_PTR_T)(0x3C100010)) /* Read data register. */
#define LCD_DBUFF (*(REG32_PTR_T)(0x3C100014)) /* Read Data buffer */
#define LCD_INTCON (*(REG32_PTR_T)(0x3C100018)) /* Interrupt control register */
#define LCD_STATUS (*(REG32_PTR_T)(0x3C10001C)) /* LCD Interface status 0106 */
#define LCD_PHTIME (*(REG32_PTR_T)(0x3C100020)) /* Phase time register 0060 */
#define LCD_RST_TIME (*(REG32_PTR_T)(0x3C100024)) /* Reset active period 07FF */
#define LCD_DRV_RST (*(REG32_PTR_T)(0x3C100028)) /* Reset drive signal */
#define LCD_WDATA (*(REG32_PTR_T)(0x3C100040)) /* Write data register FIXME */
#ifdef CPU_S5L8700
#define LCD_BASE 0x3C100000
#else /* CPU_S5L8701 */
#define LCD_BASE 0x38600000
#endif
#define LCD_CON (*(REG16_PTR_T)(LCD_BASE+0x00)) /* Control register. */
#define LCD_WCMD (*(REG16_PTR_T)(LCD_BASE+0x04)) /* Write command register. */
#define LCD_RCMD (*(REG16_PTR_T)(LCD_BASE+0x0C)) /* Read command register. */
#define LCD_RDATA (*(REG16_PTR_T)(LCD_BASE+0x10)) /* Read data register. */
#define LCD_DBUFF (*(REG16_PTR_T)(LCD_BASE+0x14)) /* Read Data buffer */
#define LCD_INTCON (*(REG16_PTR_T)(LCD_BASE+0x18)) /* Interrupt control register */
#define LCD_STATUS (*(REG16_PTR_T)(LCD_BASE+0x1C)) /* LCD Interface status 0106 */
#define LCD_PHTIME (*(REG16_PTR_T)(LCD_BASE+0x20)) /* Phase time register 0060 */
#define LCD_RST_TIME (*(REG16_PTR_T)(LCD_BASE+0x24)) /* Reset active period 07FF */
#define LCD_DRV_RST (*(REG16_PTR_T)(LCD_BASE+0x28)) /* Reset drive signal */
#define LCD_WDATA (*(REG16_PTR_T)(LCD_BASE+0x40)) /* Write data register FIXME */
/* 27. CLCD CONTROLLER */
#define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */