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Gigabeat S: Use statically initialized channel descriptors. Also, there's no need for them to be in non-cached memory since they're only used on the AP side.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27103 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2010-06-24 08:40:05 +00:00
parent 1ae6ee263b
commit c2851389b9
2 changed files with 51 additions and 39 deletions
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48
firmware/target/arm/imx31/ata-imx31.c
View file

@ -251,8 +251,33 @@ static struct wakeup ata_dma_wakeup;
/* Array of buffer descriptors for large transfers and alignnment */
static struct buffer_descriptor ata_bda[ATA_BD_COUNT] NOCACHEBSS_ATTR;
/* ATA channel descriptors */
static struct channel_descriptor ata_cd_rd NOCACHEBSS_ATTR; /* read channel */
static struct channel_descriptor ata_cd_wr NOCACHEBSS_ATTR; /* write channel */
/* Read/write channels share buffer descriptors and callbacks */
static void ata_dma_callback(void);
static struct channel_descriptor ata_cd_rd = /* read channel */
{
.bd_count = ATA_BD_COUNT,
.callback = ata_dma_callback,
.shp_addr = SDMA_PER_ADDR_ATA_RX,
.wml = SDMA_ATA_WML,
.per_type = SDMA_PER_ATA,
.tran_type = SDMA_TRAN_PER_2_EMI,
.event_id1 = SDMA_REQ_ATA_TXFER_END,
.event_id2 = SDMA_REQ_ATA_RX,
};
static struct channel_descriptor ata_cd_wr = /* write channel */
{
.bd_count = ATA_BD_COUNT,
.callback = ata_dma_callback,
.shp_addr = SDMA_PER_ADDR_ATA_TX,
.wml = SDMA_ATA_WML,
.per_type = SDMA_PER_ATA,
.tran_type = SDMA_TRAN_EMI_2_PER,
.event_id1 = SDMA_REQ_ATA_TXFER_END,
.event_id2 = SDMA_REQ_ATA_TX,
};
/* DMA channel to be started for transfer */
static unsigned int current_channel = 0;
@ -654,25 +679,6 @@ void ata_device_init(void)
/* Called for first time at startup */
wakeup_init(&ata_dma_wakeup);
/* Read/write channels share buffer descriptors */
ata_cd_rd.bd_count = ATA_BD_COUNT;
ata_cd_rd.callback = ata_dma_callback;
ata_cd_rd.shp_addr = SDMA_PER_ADDR_ATA_RX;
ata_cd_rd.wml = SDMA_ATA_WML;
ata_cd_rd.per_type = SDMA_PER_ATA;
ata_cd_rd.tran_type = SDMA_TRAN_PER_2_EMI;
ata_cd_rd.event_id1 = SDMA_REQ_ATA_TXFER_END;
ata_cd_rd.event_id2 = SDMA_REQ_ATA_RX;
ata_cd_wr.bd_count = ATA_BD_COUNT;
ata_cd_wr.callback = ata_dma_callback;
ata_cd_wr.shp_addr = SDMA_PER_ADDR_ATA_TX;
ata_cd_wr.wml = SDMA_ATA_WML;
ata_cd_wr.per_type = SDMA_PER_ATA;
ata_cd_wr.tran_type = SDMA_TRAN_EMI_2_PER;
ata_cd_wr.event_id1 = SDMA_REQ_ATA_TXFER_END;
ata_cd_wr.event_id2 = SDMA_REQ_ATA_TX;
if (!sdma_channel_init(ATA_DMA_CH_NUM_RD, &ata_cd_rd, ata_bda) ||
!sdma_channel_init(ATA_DMA_CH_NUM_WR, &ata_cd_wr, ata_bda))
{

42
firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
View file

@ -33,7 +33,18 @@
#define DMA_REC_CH_PRIORITY 6
static struct buffer_descriptor dma_play_bd NOCACHEBSS_ATTR;
static struct channel_descriptor dma_play_cd NOCACHEBSS_ATTR;
static void play_dma_callback(void);
static struct channel_descriptor dma_play_cd =
{
.bd_count = 1,
.callback = play_dma_callback,
.shp_addr = SDMA_PER_ADDR_SSI2_TX1,
.wml = SDMA_SSI_TXFIFO_WML*2,
.per_type = SDMA_PER_SSI_SHP, /* SSI2 shared with SDMA core */
.tran_type = SDMA_TRAN_EMI_2_PER,
.event_id1 = SDMA_REQ_SSI2_TX1,
};
/* The pcm locking relies on the fact the interrupt handlers run to completion
* before lower-priority modes proceed. We don't have to touch hardware
@ -123,14 +134,6 @@ void pcm_dma_apply_settings(void)
void pcm_play_dma_init(void)
{
/* Init channel information */
dma_play_cd.bd_count = 1;
dma_play_cd.callback = play_dma_callback;
dma_play_cd.shp_addr = SDMA_PER_ADDR_SSI2_TX1;
dma_play_cd.wml = SDMA_SSI_TXFIFO_WML*2;
dma_play_cd.per_type = SDMA_PER_SSI_SHP; /* SSI2 shared with SDMA core */
dma_play_cd.tran_type = SDMA_TRAN_EMI_2_PER;
dma_play_cd.event_id1 = SDMA_REQ_SSI2_TX1;
sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd);
sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY);
@ -372,7 +375,18 @@ void * pcm_dma_addr(void *addr)
#ifdef HAVE_RECORDING
static struct buffer_descriptor dma_rec_bd NOCACHEBSS_ATTR;
static struct channel_descriptor dma_rec_cd NOCACHEBSS_ATTR;
static void rec_dma_callback(void);
static struct channel_descriptor dma_rec_cd =
{
.bd_count = 1,
.callback = rec_dma_callback,
.shp_addr = SDMA_PER_ADDR_SSI1_RX1,
.wml = SDMA_SSI_RXFIFO_WML*2,
.per_type = SDMA_PER_SSI,
.tran_type = SDMA_TRAN_PER_2_EMI,
.event_id1 = SDMA_REQ_SSI1_RX1,
};
static struct dma_data dma_rec_data =
{
@ -495,14 +509,6 @@ void pcm_rec_dma_init(void)
pcm_rec_dma_stop();
/* Init channel information */
dma_rec_cd.bd_count = 1;
dma_rec_cd.callback = rec_dma_callback;
dma_rec_cd.shp_addr = SDMA_PER_ADDR_SSI1_RX1;
dma_rec_cd.wml = SDMA_SSI_RXFIFO_WML*2;
dma_rec_cd.per_type = SDMA_PER_SSI;
dma_rec_cd.tran_type = SDMA_TRAN_PER_2_EMI;
dma_rec_cd.event_id1 = SDMA_REQ_SSI1_RX1;
sdma_channel_init(DMA_REC_CH_NUM, &dma_rec_cd, &dma_rec_bd);
sdma_channel_set_priority(DMA_REC_CH_NUM, DMA_REC_CH_PRIORITY);
}