From c249dea2b72e2e510cd6599054fa6d22fa868645 Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Thu, 14 Nov 2024 17:22:46 +0000 Subject: [PATCH] libsetjmp: fix unpredictable behavior warning on ARM Cortex-M GAS warns about unpredictable behavior of "ldr sp, [a1], #4" that exists on Cortex-M3 (errata 752419) but this warning is incorrectly issued on other cores too (eg, Cortex-M7). Since the fix is just one extra instruction we may as well apply the workaround for all Cortex-M targets. Change-Id: I0c2aa46837f776d67d0236b627af1572aa5ab307 --- lib/libsetjmp/arm/setjmp.S | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/lib/libsetjmp/arm/setjmp.S b/lib/libsetjmp/arm/setjmp.S index ee5ebd9169..75f6f1ec8f 100644 --- a/lib/libsetjmp/arm/setjmp.S +++ b/lib/libsetjmp/arm/setjmp.S @@ -151,7 +151,18 @@ SYM (\name): /* Restore the registers, retrieving the state when setjmp() was called. */ #ifdef __thumb2__ ldmfd a1!, { v1-v7, fp, ip, lr } - ldr sp, [a1],#+4 +#if __ARM_ARCH_PROFILE == 'M' + /* + * Errata 752419: Interrupted loads to SP can cause erroneous behaviour + * Apply the suggested workaround of loading to an intermediate register + * and then moving into sp. This only affects Cortex-M3 but a warning is + * issued by the assembler for all armv7-m targets with binutils 2.38. + */ + ldr a3, [a1], #4 + mov sp, a3 +#else + ldr sp, [a1], #4 +#endif #else ldmfd a1!, { v1-v7, fp, ip, sp, lr } #endif