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x1000: Trim unused cache functions from the SPL build

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Change-Id: Ib645d8ff10cfc672de8ac2debaa17d7dd50dfafb
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Aidan MacDonald 2021-04-07 23:14:35 +01:00 • committed by Solomon Peachy
parent 54b8e9131c
commit c0a823e2ab
1 changed files with 9 additions and 0 deletions
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9
firmware/target/mips/ingenic_x1000/system-target.h
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@ -28,6 +28,15 @@
#define CACHEALIGN_BITS 5 #define CACHEALIGN_BITS 5
#define CACHE_SIZE (16*1024) #define CACHE_SIZE (16*1024)
#ifdef BOOTLOADER_SPL
/* This saves ~200 bytes in the SPL by allowing -ffunction-sections to split
* up the cache management functions, most of which aren't called by the SPL.
* If they are placed in .icode, then they all end up in one section and the
* linker can't discard the unused functions.
*/
# define MIPS_CACHEFUNC_ATTR
#endif
#include "mmu-mips.h" #include "mmu-mips.h"
#include "mipsregs.h" #include "mipsregs.h"
#include "mipsr2-endian.h" #include "mipsr2-endian.h"