diff --git a/firmware/target/arm/as3525/ata_sd_as3525.c b/firmware/target/arm/as3525/ata_sd_as3525.c
index 472e0fe09a..ab247c86d9 100644
--- a/firmware/target/arm/as3525/ata_sd_as3525.c
+++ b/firmware/target/arm/as3525/ata_sd_as3525.c
@@ -121,6 +121,10 @@ static struct event_queue sd_queue;
 bool sd_enabled = false;
 #endif
 
+#if defined(HAVE_MULTIDRIVE)
+static bool hs_card = false;
+#endif
+
 static struct wakeup transfer_completion_signal;
 static volatile unsigned int transfer_error[NUM_VOLUMES];
 #define PL180_MAX_TRANSFER_ERRORS 10
@@ -347,13 +351,18 @@ static int sd_init_card(const int drive)
 
     sd_parse_csd(&card_info[drive]);
 
+#if defined(HAVE_MULTIDRIVE)
+    hs_card = (card_info[drive].speed == 50000000) ? true : false;
+#endif
+
     /* Boost MCICLK to operating speed */
     if(drive == INTERNAL_AS3525)
-        MCI_CLOCK(drive) = MCI_QUARTERSPEED;  /* MCICLK = PCLK/4 = 15.5MHz  */
+        MCI_CLOCK(drive) = MCI_HALFSPEED;  /* MCICLK = IDE_CLK/2 = 25 MHz  */
+#if defined(HAVE_MULTIDRIVE)
     else
         /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
-        MCI_CLOCK(drive) = ((card_info[drive].speed == 50000000) ?
-                                              MCI_HALFSPEED : MCI_QUARTERSPEED);
+        MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
+#endif
 
     /*  CMD7 w/rca: Select card to put it in TRAN state */
     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
@@ -733,10 +742,14 @@ static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
-
+#if defined(HAVE_MULTIDRIVE)
             /*Small delay for writes prevents data crc failures at lower freqs*/
-            int write_delay = 125;
-            while(write_delay--);
+            if((drive == SD_SLOT_AS3525) && !hs_card)
+            {
+                int write_delay = 125;
+                while(write_delay--);
+            }
+#endif
         }
         else
             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 81926c1884..bc112fdea8 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -118,9 +118,8 @@
 
 #define AS3525_IDE_SEL           AS3525_CLK_PLLA           /* Input Source   */
 #define AS3525_IDE_DIV           (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
-#define AS3525_IDE_FREQ          90000000    /* The OF uses 66MHz maximal freq
-                                               but sd transfers fail on some
-                                               players with this limit */
+#define AS3525_IDE_FREQ          50000000    /* The OF uses 66MHz maximal freq */
+
 
 //#define AS3525_USB_SEL           AS3525_CLK_PLLA            /* Input Source   */
 //#define AS3525_USB_DIV           /* div = 1/(n=0?1:2n)*/
diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c
index 2606f68e82..f8f183d432 100644
--- a/firmware/target/arm/as3525/debug-as3525.c
+++ b/firmware/target/arm/as3525/debug-as3525.c
@@ -185,9 +185,9 @@ int calc_freq(int clk)
             if(!(MCI_NAND & (1<<8)))
                 return 0;
             else if(MCI_NAND & (1<<10))
-                return calc_freq(CLK_PCLK);
+                return calc_freq(CLK_IDE);
             else
-                return calc_freq(CLK_PCLK)/(((MCI_NAND & 0xff)+1)*2);
+                return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2);
         case CLK_SD_MCLK_MSD:
             if(!(MCI_SD & (1<<8)))
                 return 0;
@@ -304,7 +304,7 @@ bool __dbg_hw_info(void)
         }
 
         lcd_putsf(0, line++, "SD  :%3dMHz    %3dMHz",
-            ((AS3525_PCLK_FREQ/ 1000000) /
+            ((AS3525_IDE_FREQ/ 1000000) /
             ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))),
             calc_freq(CLK_SD_MCLK_NAND)/1000000);
 #ifdef HAVE_MULTIDRIVE