arm: add ARM Cortex-M register definitions

Change-Id: Ifb90606d2b6c94c4f91798a41415c895e2888520

firmware/target/arm/cortex-m/nvic.h

@@ -0,0 +1,70 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 3.0.0
+ * cortex_m7 version: 1.0
+ * cortex_m7 authors: Aidan MacDonald
+ *
+ * Copyright (C) 2015 by the authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __ARM_CORTEX_M_NVIC_H__
+#define __ARM_CORTEX_M_NVIC_H__
+
+#include "macro.h"
+
+#define REG_NVIC_ISER(_n1)  cm_reg(NVIC_ISER(_n1))
+#define CMA_NVIC_ISER(_n1)  (0xe000e000 + 0x100 + (_n1) * 0x4)
+#define CMT_NVIC_ISER(_n1)  CMIO_32_RW
+#define CMN_NVIC_ISER(_n1)  NVIC_ISER
+
+#define REG_NVIC_ICER(_n1)  cm_reg(NVIC_ICER(_n1))
+#define CMA_NVIC_ICER(_n1)  (0xe000e000 + 0x180 + (_n1) * 0x4)
+#define CMT_NVIC_ICER(_n1)  CMIO_32_RW
+#define CMN_NVIC_ICER(_n1)  NVIC_ICER
+
+#define REG_NVIC_ISPR(_n1)  cm_reg(NVIC_ISPR(_n1))
+#define CMA_NVIC_ISPR(_n1)  (0xe000e000 + 0x200 + (_n1) * 0x4)
+#define CMT_NVIC_ISPR(_n1)  CMIO_32_RW
+#define CMN_NVIC_ISPR(_n1)  NVIC_ISPR
+
+#define REG_NVIC_ICPR(_n1)  cm_reg(NVIC_ICPR(_n1))
+#define CMA_NVIC_ICPR(_n1)  (0xe000e000 + 0x280 + (_n1) * 0x4)
+#define CMT_NVIC_ICPR(_n1)  CMIO_32_RW
+#define CMN_NVIC_ICPR(_n1)  NVIC_ICPR
+
+#define REG_NVIC_IABR(_n1)  cm_reg(NVIC_IABR(_n1))
+#define CMA_NVIC_IABR(_n1)  (0xe000e000 + 0x300 + (_n1) * 0x4)
+#define CMT_NVIC_IABR(_n1)  CMIO_32_RW
+#define CMN_NVIC_IABR(_n1)  NVIC_IABR
+
+#define REG_NVIC_IPR(_n1)   cm_reg(NVIC_IPR(_n1))
+#define CMA_NVIC_IPR(_n1)   (0xe000e000 + 0x400 + (_n1) * 0x4)
+#define CMT_NVIC_IPR(_n1)   CMIO_32_RW
+#define CMN_NVIC_IPR(_n1)   NVIC_IPR
+
+#define REG_NVIC_STIR               cm_reg(NVIC_STIR)
+#define CMA_NVIC_STIR               (0xe000e000 + 0xf00)
+#define CMT_NVIC_STIR               CMIO_32_RW
+#define CMN_NVIC_STIR               NVIC_STIR
+#define BP_NVIC_STIR_INTID          0
+#define BM_NVIC_STIR_INTID          0x1ff
+#define BF_NVIC_STIR_INTID(v)       (((v) & 0x1ff) << 0)
+#define BFM_NVIC_STIR_INTID(v)      BM_NVIC_STIR_INTID
+#define BF_NVIC_STIR_INTID_V(e)     BF_NVIC_STIR_INTID(BV_NVIC_STIR_INTID__##e)
+#define BFM_NVIC_STIR_INTID_V(v)    BM_NVIC_STIR_INTID
+
+#endif /* __ARM_CORTEX_M_NVIC_H__*/