mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-12-08 12:45:26 -05:00
Move usb-s3c6400 register comments to usb-s3c6400.h
Use common defines in usb-s3c6400.c and usb-drv-as3525v2.c No functional changes git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31220 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré
parent
62e0cdca26
commit
bc943a06ba
5 changed files with 346 additions and 572 deletions
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@ -36,6 +36,14 @@
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#include "usb-drv-as3525v2.h"
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#include "usb_core.h"
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/* Number of IN/OUT endpoints */
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#define NUM_IN_EP 3
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#define NUM_OUT_EP 2
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/* List of IN enpoints */
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#define IN_EP_LIST 0, 3, 5
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#define OUT_EP_LIST 2, 4
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static const uint8_t in_ep_list[NUM_IN_EP + 1] = {0, IN_EP_LIST};
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static const uint8_t out_ep_list[NUM_OUT_EP + 1] = {0, OUT_EP_LIST};
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@ -216,7 +224,7 @@ static void prepare_setup_ep0(void)
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{
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logf("usb-drv: prepare EP0");
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/* setup DMA */
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DOEPDMA(0) = (unsigned long)AS3525_PHYSICAL_ADDR(&_ep0_setup_pkt);
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DOEPDMA(0) = (void*)AS3525_PHYSICAL_ADDR(&_ep0_setup_pkt);
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/* Setup EP0 OUT with the following parameters:
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* packet count = 1
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@ -408,7 +416,7 @@ static void core_dev_init(void)
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/* Setup FIFOs */
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GRXFSIZ = 512;
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GNPTXFSIZ = MAKE_FIFOSIZE_DATA(512, 512);
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GNPTXFSIZ = MAKE_FIFOSIZE_DATA(512);
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/* Setup interrupt masks for endpoints */
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/* Setup interrupt masks */
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@ -766,9 +774,9 @@ static int usb_drv_transfer(int ep, void *ptr, int len, bool dir_in, bool blocki
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/* disable interrupts to avoid any race */
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int oldlevel = disable_irq_save();
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volatile unsigned long *epctl = dir_in ? &DIEPCTL(ep) : &DOEPCTL(ep);
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volatile unsigned long *eptsiz = dir_in ? &DIEPTSIZ(ep) : &DOEPTSIZ(ep);
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volatile unsigned long *epdma = dir_in ? &DIEPDMA(ep) : &DOEPDMA(ep);
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volatile uint32_t *epctl = dir_in ? &DIEPCTL(ep) : &DOEPCTL(ep);
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volatile uint32_t *eptsiz = dir_in ? &DIEPTSIZ(ep) : &DOEPTSIZ(ep);
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const void * volatile * epdma = dir_in ? &DIEPDMA(ep) : &DOEPDMA(ep);
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struct usb_endpoint *endpoint = &endpoints[ep][dir_in];
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#define DEPCTL *epctl
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#define DEPTSIZ *eptsiz
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@ -790,12 +798,12 @@ static int usb_drv_transfer(int ep, void *ptr, int len, bool dir_in, bool blocki
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if(len == 0)
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{
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DEPDMA = 0x10000000;
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DEPDMA = (void*)0x10000000;
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DEPTSIZ = 1 << DEPTSIZ_pkcnt_bitp;
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}
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else
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{
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DEPDMA = (unsigned long)AS3525_PHYSICAL_ADDR(ptr);
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DEPDMA = (void*)AS3525_PHYSICAL_ADDR(ptr);
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DEPTSIZ = (nb_packets << DEPTSIZ_pkcnt_bitp) | len;
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if(dir_in)
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clean_dcache_range(ptr, len);
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@ -22,149 +22,12 @@
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#define __USB_DRV_AS3525v2_H__
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#include "as3525v2.h"
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/* All multi-bit fields in the driver use the following convention.
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* If the register name is NAME, then there is one define NAME_bitp
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* which holds the bit position and one define NAME_bits which holds
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* a mask of the bits within the register (after shift).
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* These macros allow easy access and construction of such fields */
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/* Usage:
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* - extract(reg_name,field_name)
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* extract a field of the register
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* - bitm(reg_name,field_name)
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* build a bitmask for the field
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*/
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#define extract(reg_name, field_name) \
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((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits)
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#define bitm(reg_name, field_name) \
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(reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp)
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#define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */
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#include "usb-s3c6400x.h"
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/**
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* Core Global Registers
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* Registers not present in usb-s3c6400
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*/
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#define BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset))
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/** OTG Control and Status Register */
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#define GOTGCTL BASE_REG(0x000)
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/** OTG Interrupt Register */
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#define GOTGINT BASE_REG(0x004)
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/** Core AHB Configuration Register */
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#define GAHBCFG BASE_REG(0x008)
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#define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */
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#define GAHBCFG_hburstlen_bitp 1
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#define GAHBCFG_hburstlen_bits 0xf
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#define GAHBCFG_INT_DMA_BURST_SINGLE 0
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#define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */
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#define GAHBCFG_INT_DMA_BURST_INCR4 3
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#define GAHBCFG_INT_DMA_BURST_INCR8 5
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#define GAHBCFG_INT_DMA_BURST_INCR16 7
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#define GAHBCFG_dma_enable (1 << 5) /** Enable DMA */
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/** Core USB Configuration Register */
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#define GUSBCFG BASE_REG(0x00C)
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#define GUSBCFG_toutcal_bitp 0
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#define GUSBCFG_toutcal_bits 0x7
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#define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */
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#define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */
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#define GUSBCFG_fsintf (1 << 5)
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#define GUSBCFG_physel (1 << 6)
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#define GUSBCFG_ddrsel (1 << 7)
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#define GUSBCFG_srpcap (1 << 8)
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#define GUSBCFG_hnpcapp (1 << 9)
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#define GUSBCFG_usbtrdtim_bitp 10
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#define GUSBCFG_usbtrdtim_bits 0xf
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#define GUSBCFG_nptxfrwnden (1 << 14)
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#define GUSBCFG_phylpwrclksel (1 << 15)
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#define GUSBCFG_otgutmifssel (1 << 16)
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#define GUSBCFG_ulpi_fsls (1 << 17)
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#define GUSBCFG_ulpi_auto_res (1 << 18)
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#define GUSBCFG_ulpi_clk_sus_m (1 << 19)
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#define GUSBCFG_ulpi_ext_vbus_drv (1 << 20)
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#define GUSBCFG_ulpi_int_vbus_indicator (1 << 21)
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#define GUSBCFG_term_sel_dl_pulse (1 << 22)
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#define GUSBCFG_force_host_mode (1 << 29)
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#define GUSBCFG_force_device_mode (1 << 30)
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#define GUSBCFG_corrupt_tx_packet (1 << 31)
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/** Core Reset Register */
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#define GRSTCTL BASE_REG(0x010)
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#define GRSTCTL_csftrst (1 << 0) /** Core soft reset */
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#define GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */
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#define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */
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#define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */
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#define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */
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#define GRSTCTL_txfnum_bitp 6 /** TxFIFO Number */
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#define GRSTCTL_txfnum_bits 0x1f
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#define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/
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/** Core Interrupt Register */
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#define GINTSTS BASE_REG(0x014)
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/* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */
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#define GINTSTS_curmode (1 << 0) /** Current mode, 0 for device */
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/** Core Interrupt Mask Register */
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#define GINTMSK BASE_REG(0x018)
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#define GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */
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#define GINTMSK_otgintr (1 << 2)
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#define GINTMSK_sofintr (1 << 3)
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#define GINTMSK_rxstsqlvl (1 << 4)
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#define GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */
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#define GINTMSK_ginnakeff (1 << 6)
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#define GINTMSK_goutnakeff (1 << 7)
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#define GINTMSK_i2cintr (1 << 9)
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#define GINTMSK_erlysuspend (1 << 10)
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#define GINTMSK_usbsuspend (1 << 11) /** USB suspend */
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#define GINTMSK_usbreset (1 << 12) /** USB reset */
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#define GINTMSK_enumdone (1 << 13) /** Enumeration done */
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#define GINTMSK_isooutdrop (1 << 14)
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#define GINTMSK_eopframe (1 << 15)
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#define GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */
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#define GINTMSK_inepintr (1 << 18) /** in pending ? */
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#define GINTMSK_outepintr (1 << 19) /** out pending ? */
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#define GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */
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#define GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */
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#define GINTMSK_portintr (1 << 24) /** Port status change ? */
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#define GINTMSK_hcintr (1 << 25)
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#define GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */
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#define GINTMSK_conidstschng (1 << 28)
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#define GINTMSK_disconnect (1 << 29) /** Disconnect */
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#define GINTMSK_sessreqintr (1 << 30) /** Session request */
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#define GINTMSK_wkupintr (1 << 31) /** Wake up */
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/** Receive Status Debug Read Register (Read Only) */
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#define GRXSTSR BASE_REG(0x01C)
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/** Receive Status Read /Pop Register (Read Only) */
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#define GRXSTSP BASE_REG(0x020)
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/** Receive FIFO Size Register */
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#define GRXFSIZ BASE_REG(0x024)
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/** Periodic Transmit FIFO Size Register */
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#define GNPTXFSIZ BASE_REG(0x028)
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/** Non-Periodic Transmit FIFO/Queue Status Register */
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#define GNPTXSTS BASE_REG(0x02C)
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/** I2C Access Register */
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#define GI2CCTL BASE_REG(0x030)
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/** PHY Vendor Control Register */
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#define GPVNDCTL BASE_REG(0x034)
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/** General Purpose Input/Output Register */
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#define GGPIO BASE_REG(0x038)
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/** User ID Register */
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#define GUID BASE_REG(0x03C)
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/** Synopsys ID Register */
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#define GSNPSID BASE_REG(0x040)
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#define BASE_REG(offset) (*(volatile uint32_t*)(OTGBASE + offset))
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/** User HW Config1 Register */
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#define GHWCFG1 BASE_REG(0x044)
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@ -203,261 +66,10 @@
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#define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */
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#define GHWCFG4_num_in_ep_bits 0xf
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/* 1<=ep<=15, don't use ep=0 !!! */
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/** Device IN Endpoint Transmit FIFO (ep) Size Register */
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#define DIEPTXFSIZ(ep) BASE_REG(0x100 + 4 * (ep))
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/** Build the content of a FIFO size register like DIEPTXFSIZ(i) and GNPTXFSIZ*/
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#define MAKE_FIFOSIZE_DATA(startadr, depth) \
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(((startadr) & 0xffff) | ((depth) << 16))
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/** Retrieve fifo size for such registers */
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#define GET_FIFOSIZE_DEPTH(data) \
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((data) >> 16)
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/** Retrieve fifo start address for such registers */
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#define GET_FIFOSIZE_START_ADR(data) \
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((data) & 0xffff)
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/**
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* Device Registers Base Addresses
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*/
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#define DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset))
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/** Device Configuration Register */
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#define DCFG DEV_REG(0x00)
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#define DCFG_devspd_bitp 0 /** Device Speed */
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#define DCFG_devspd_bits 0x3
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#define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */
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#define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */
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#define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */
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#define DCFG_devadr_bitp 4 /** Device Address */
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#define DCFG_devadr_bits 0x7f
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#define DCFG_perfrint_bitp 11 /** Periodic Frame Interval */
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#define DCFG_perfrint_bits 0x3
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#define DCFG_FRAME_INTERVAL_80 0
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#define DCFG_FRAME_INTERVAL_85 1
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#define DCFG_FRAME_INTERVAL_90 2
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#define DCFG_FRAME_INTERVAL_95 3
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/** Device Control Register */
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#define DCTL DEV_REG(0x04)
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#define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */
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#define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */
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#define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */
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#define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */
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#define DCTL_tstctl_bitp 4 /** Test Control */
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#define DCTL_tstctl_bits 0x7
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#define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */
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#define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */
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#define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */
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#define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */
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#define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */
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/** Device Status Register */
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#define DSTS DEV_REG(0x08)
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#define DSTS_suspsts (1 << 0) /** Suspend status */
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#define DSTS_enumspd_bitp 1 /** Enumerated speed */
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#define DSTS_enumspd_bits 0x3
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#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
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#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
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#define DSTS_ENUMSPD_LS_PHY_6MHZ 2
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#define DSTS_ENUMSPD_FS_PHY_48MHZ 3
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#define DSTS_errticerr (1 << 3) /** Erratic errors ? */
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#define DSTS_soffn_bitp 8 /** Frame or Microframe Number of the received SOF */
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#define DSTS_soffn_bits 0x3fff
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/** Device IN Endpoint Common Interrupt Mask Register */
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#define DIEPMSK DEV_REG(0x10)
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/* the following apply to DIEPMSK and DIEPINT */
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#define DIEPINT_xfercompl (1 << 0) /** Transfer complete */
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#define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */
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#define DIEPINT_ahberr (1 << 2) /** AHB error */
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#define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */
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#define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */
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#define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */
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#define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */
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#define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */
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#define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */
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/** Device OUT Endpoint Common Interrupt Mask Register */
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#define DOEPMSK DEV_REG(0x14)
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/* the following apply to DOEPMSK and DOEPINT */
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#define DOEPINT_xfercompl (1 << 0) /** Transfer complete */
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#define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */
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#define DOEPINT_ahberr (1 << 2) /** AHB error */
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#define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/
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/** Device All Endpoints Interrupt Register */
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#define DAINT DEV_REG(0x18)
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/* valid for DAINT and DAINTMSK, for 0<=ep<=15 */
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#define DAINT_IN_EP(i) (1 << (i))
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#define DAINT_OUT_EP(i) (1 << ((i) + 16))
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/** Device Endpoints Interrupt Mask Register */
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#define DAINTMSK DEV_REG(0x1C)
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/** Device IN Token Sequence Learning Queue Read Register 1 */
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#define DTKNQR1 DEV_REG(0x20)
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/** Device IN Token Sequence Learning Queue Register 2 */
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#define DTKNQR2 DEV_REG(0x24)
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/** Device IN Token Queue Pop register */
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#define DTKNQP DEV_REG(0x28)
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/* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h.
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* the previous registers exists but has a different name :( */
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/** Device VBUS discharge register*/
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#define DVBUSDIS DEV_REG(0x28)
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/** Device VBUS pulse register */
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#define DVBUSPULSE DEV_REG(0x2C)
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/** Device IN Token Queue Read Register 3 (RO) */
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#define DTKNQR3 DEV_REG(0x30)
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/** Device Thresholding control register */
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#define DTHRCTL DEV_REG(0x30)
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#define DTHRCTL_non_iso_thr_en (1 << 0)
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#define DTHRCTL_iso_thr_en (1 << 1)
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#define DTHRCTL_tx_thr_len_bitp 2
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#define DTHRCTL_tx_thr_len_bits 0x1FF
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#define DTHRCTL_rx_thr_en (1 << 16)
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#define DTHRCTL_rx_thr_len_bitp 17
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#define DTHRCTL_rx_thr_len_bits 0x1FF
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/** Device IN Token Queue Read Register 4 (RO) */
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#define DTKNQR4 DEV_REG(0x34)
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/** Device IN EPs empty Inr. Mask Register */
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#define FFEMPTYMSK DEV_REG(0x34)
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#define PCGCCTL BASE_REG(0xE00) /** Power and Clock Gating Control Register */
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/** Device IN Endpoint (ep) Control Register */
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#define DIEPCTL(ep) DEV_REG(0x100 + (ep) * 0x20)
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/** Device OUT Endpoint (ep) Control Register */
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#define DOEPCTL(ep) DEV_REG(0x300 + (ep) * 0x20)
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/** Maximum Packet Size
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* IN/OUT EPn
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* IN/OUT EP0 - 2 bits
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* 2'b00: 64 Bytes
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* 2'b01: 32
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* 2'b10: 16
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* 2'b11: 8 */
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#define DEPCTL_mps_bitp 0
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#define DEPCTL_mps_bits 0x7ff
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#define DEPCTL_MPS_64 0
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#define DEPCTL_MPS_32 1
|
||||
#define DEPCTL_MPS_16 2
|
||||
#define DEPCTL_MPS_8 3
|
||||
/** Next Endpoint
|
||||
* IN EPn/IN EP0
|
||||
* OUT EPn/OUT EP0 - reserved */
|
||||
#define DEPCTL_nextep_bitp 11
|
||||
#define DEPCTL_nextep_bits 0xf
|
||||
#define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */
|
||||
/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
|
||||
* This field contains the PID of the packet going to
|
||||
* be received or transmitted on this endpoint. The
|
||||
* application should program the PID of the first
|
||||
* packet going to be received or transmitted on this
|
||||
* endpoint , after the endpoint is
|
||||
* activated. Application use the SetD1PID and
|
||||
* SetD0PID fields of this register to program either
|
||||
* D0 or D1 PID.
|
||||
*
|
||||
* The encoding for this field is
|
||||
* - 0: D0
|
||||
* - 1: D1
|
||||
*/
|
||||
#define DEPCTL_dpid (1 << 16)
|
||||
#define DEPCTL_naksts (1 << 17) /** NAK Status */
|
||||
/** Endpoint Type
|
||||
* 2'b00: Control
|
||||
* 2'b01: Isochronous
|
||||
* 2'b10: Bulk
|
||||
* 2'b11: Interrupt */
|
||||
#define DEPCTL_eptype_bitp 18
|
||||
#define DEPCTL_eptype_bits 0x3
|
||||
/** Snoop Mode
|
||||
* OUT EPn/OUT EP0
|
||||
* IN EPn/IN EP0 - reserved */
|
||||
#define DEPCTL_snp (1 << 20)
|
||||
#define DEPCTL_stall (1 << 21) /** Stall Handshake */
|
||||
/** Tx Fifo Number
|
||||
* IN EPn/IN EP0
|
||||
* OUT EPn/OUT EP0 - reserved */
|
||||
#define DEPCTL_txfnum_bitp 22
|
||||
#define DEPCTL_txfnum_bits 0xf
|
||||
|
||||
#define DEPCTL_cnak (1 << 26) /** Clear NAK */
|
||||
#define DEPCTL_snak (1 << 27) /** Set NAK */
|
||||
/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
|
||||
* Writing to this field sets the Endpoint DPID (DPID)
|
||||
* field in this register to DATA0. Set Even
|
||||
* (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
|
||||
* Writing to this field sets the Even/Odd
|
||||
* (micro)frame (EO_FrNum) field to even (micro)
|
||||
* frame.
|
||||
*/
|
||||
#define DEPCTL_setd0pid (1 << 28)
|
||||
/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
|
||||
* Writing to this field sets the Endpoint DPID (DPID)
|
||||
* field in this register to DATA1 Set Odd
|
||||
* (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
|
||||
* Writing to this field sets the Even/Odd
|
||||
* (micro)frame (EO_FrNum) field to odd (micro) frame.
|
||||
*/
|
||||
#define DEPCTL_setd1pid (1 << 29)
|
||||
#define DEPCTL_epdis (1 << 30) /** Endpoint disable */
|
||||
#define DEPCTL_epena (1 << 31) /** Endpoint enable */
|
||||
|
||||
/** Device IN Endpoint (ep) Transfer Size Register */
|
||||
#define DIEPTSIZ(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x10)
|
||||
/** Device OUT Endpoint (ep) Transfer Size Register */
|
||||
#define DOEPTSIZ(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x10)
|
||||
|
||||
/* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
|
||||
#define DEPTSIZ_xfersize_bitp 0 /** Transfer Size */
|
||||
#define DEPTSIZ_xfersize_bits 0x7ffff
|
||||
#define DEPTSIZ_pkcnt_bitp 19 /** Packet Count */
|
||||
#define DEPTSIZ_pkcnt_bits 0x3ff
|
||||
#define DEPTSIZ_mc_bitp 29 /** Multi Count - Periodic IN endpoints */
|
||||
#define DEPTSIZ_mc_bits 0x3
|
||||
|
||||
/* idem but for i=0 */
|
||||
#define DEPTSIZ0_xfersize_bitp 0 /** Transfer Size */
|
||||
#define DEPTSIZ0_xfersize_bits 0x7f
|
||||
#define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */
|
||||
#define DEPTSIZ0_pkcnt_bits 0x3
|
||||
#define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */
|
||||
#define DEPTSIZ0_supcnt_bits 0x3
|
||||
|
||||
/** Device IN Endpoint (ep) Interrupt Register */
|
||||
#define DIEPINT(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x8)
|
||||
/** Device IN Endpoint (ep) DMA Address Register */
|
||||
#define DIEPDMA(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x14)
|
||||
/** Device IN Endpoint (ep) Transmit FIFO Status Register */
|
||||
#define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18)
|
||||
#define DTXFSTS(ep) (*((const void* volatile*)(OTGBASE + 0x918 + 0x20 * (x))))
|
||||
|
||||
/** Device OUT Endpoint (ep) Frame number Register */
|
||||
#define DOEPFN(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x4)
|
||||
/** Device Endpoint (ep) Interrupt Register */
|
||||
#define DOEPINT(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x8)
|
||||
/** Device Endpoint (ep) DMA Address Register */
|
||||
#define DOEPDMA(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x14)
|
||||
|
||||
/**
|
||||
* Parameters
|
||||
*/
|
||||
|
||||
/* Number of IN/OUT endpoints */
|
||||
#define NUM_IN_EP 3
|
||||
#define NUM_OUT_EP 2
|
||||
|
||||
/* List of IN enpoints */
|
||||
#define IN_EP_LIST 1, 3, 5
|
||||
#define OUT_EP_LIST 2, 4
|
||||
#define DOEPFN(ep) (*((const void* volatile*)(OTGBASE + 0xB04 + 0x20 * (x))))
|
||||
|
||||
#endif /* __USB_DRV_AS3525v2_H__ */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue