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iPod Nano 2G: Dynamic Vcore scaling, based on current CPU clock. Adds 1-2 hours of battery life.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28590 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann 2010-11-14 15:20:06 +00:00
parent 81381a36b4
commit bbebaa406f
1 changed files with 8 additions and 33 deletions
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41
firmware/target/arm/s5l8700/system-s5l8700.c
View file

@ -203,16 +203,17 @@ void set_cpu_frequency(long frequency)
if (cpu_frequency == frequency) if (cpu_frequency == frequency)
return; return;
int oldlevel = disable_irq_save();
#if 1
if (frequency == CPUFREQ_MAX) if (frequency == CPUFREQ_MAX)
{ {
/* Vcore = 1.000V */
pmu_write(0x1e, 0xf);
/* Allow for voltage to stabilize */
sleep(HZ / 100);
/* FCLK_CPU = PLL0, HCLK = PLL0 / 2 */ /* FCLK_CPU = PLL0, HCLK = PLL0 / 2 */
CLKCON = (CLKCON & ~0xFF00FF00) | 0x20003100; CLKCON = (CLKCON & ~0xFF00FF00) | 0x20003100;
/* PCLK = HCLK / 2 */ /* PCLK = HCLK / 2 */
CLKCON2 |= 0x200; CLKCON2 |= 0x200;
/* Switch to ASYNCHRONOUS mode */ /* Switch to ASYNCHRONOUS mode => GCLK = FCLK_CPU */
asm volatile( asm volatile(
"mrc p15, 0, r0,c1,c0 \n\t" "mrc p15, 0, r0,c1,c0 \n\t"
"orr r0, r0, #0xc0000000 \n\t" "orr r0, r0, #0xc0000000 \n\t"
@ -222,7 +223,7 @@ void set_cpu_frequency(long frequency)
} }
else else
{ {
/* Switch to FASTBUS mode */ /* Switch to FASTBUS mode => GCLK = HCLK */
asm volatile( asm volatile(
"mrc p15, 0, r0,c1,c0 \n\t" "mrc p15, 0, r0,c1,c0 \n\t"
"bic r0, r0, #0xc0000000 \n\t" "bic r0, r0, #0xc0000000 \n\t"
@ -233,37 +234,11 @@ void set_cpu_frequency(long frequency)
CLKCON2 &= ~0x200; CLKCON2 &= ~0x200;
/* FCLK_CPU = OFF, HCLK = PLL0 / 4 */ /* FCLK_CPU = OFF, HCLK = PLL0 / 4 */
CLKCON = (CLKCON & ~0xFF00FF00) | 0x80003300; CLKCON = (CLKCON & ~0xFF00FF00) | 0x80003300;
/* Vcore = 0.900V */
pmu_write(0x1e, 0xb);
} }
#else /* Alternative: Also clock down the PLL. Doesn't seem to save much
current, but results in high switching latency. */
if (frequency == CPUFREQ_MAX)
{
CLKCON &= ~0xFF00FF00; /* Everything back to the OSC */
PLLCON &= ~1; /* Power down PLL0 */
PLL0PMS = 0x021200; /* 192 MHz */
PLL0LCNT = 8100;
PLLCON |= 1; /* Power up PLL0 */
while (!(PLLLOCK & 1)); /* Wait for PLL to lock */
CLKCON2 |= 0x200; /* PCLK = HCLK / 2 */
CLKCON |= 0x20003100; /* FCLK_CPU = PLL0, PCLK = PLL0 / 2 */
}
else
{
CLKCON &= ~0xFF00FF00; /* Everything back to the OSC */
CLKCON2 &= ~0x200; /* PCLK = HCLK */
PLLCON &= ~1; /* Power down PLL0 */
PLL0PMS = 0x000500; /* 48 MHz */
PLL0LCNT = 8100;
PLLCON |= 1; /* Power up PLL0 */
while (!(PLLLOCK & 1)); /* Wait for PLL to lock */
CLKCON |= 0x20002000; /* FCLK_CPU = PLL0, PCLK = PLL0 */
}
#endif
cpu_frequency = frequency; cpu_frequency = frequency;
restore_irq(oldlevel);
} }
#endif #endif