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Coldfire targets: enable buffered writes by default. Speeds up all sorts of I/O that writes to ports: LCD update (except the functions using DMA on H300), ATA writes, .... Some timings had to be adjusted for the new configuration.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15129 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2007-10-15 21:16:50 +00:00
parent c08c081211
commit b85b6be3aa
7 changed files with 16 additions and 16 deletions
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4
firmware/target/coldfire/crt0.S
View file

@ -218,8 +218,8 @@ start:
move.l #0x01000000,%d0 move.l #0x01000000,%d0
movec.l %d0,%cacr movec.l %d0,%cacr
/* Enable cache, default=non-cacheable,no buffered writes */ /* Enable cache, default=non-cacheable, buffered writes */
move.l #0x80000000,%d0 move.l #0x80000100,%d0
movec.l %d0,%cacr movec.l %d0,%cacr
/* Cache enabled in SDRAM only, buffered writes enabled */ /* Cache enabled in SDRAM only, buffered writes enabled */

6
firmware/target/coldfire/iaudio/m5/lcd-as-m5.S
View file

@ -70,13 +70,13 @@ lcd_write_data:
lea 0xf0008002, %a1 lea 0xf0008002, %a1
.loop: .loop:
/* When running in IRAM, this loop takes 7 cycles plus the LCD write. /* When running in IRAM, this loop takes 10 cycles plus the LCD write.
The 7 cycles are necessary to follow the LCD timing specs The 10 cycles are necessary to follow the LCD timing specs
at 140MHz */ at 140MHz */
nop /* 3(0/0) */
move.b (%a0)+, %d1 /* 3(1/0) */ move.b (%a0)+, %d1 /* 3(1/0) */
move.w %d1, (%a1) /* 1(0/1) */ move.w %d1, (%a1) /* 1(0/1) */
subq.l #1, %d0 /* 1(0/0) */ subq.l #1, %d0 /* 1(0/0) */
nop /* 1(0/0) */
bne .loop /* 2(0/0) */ bne .loop /* 2(0/0) */
rts rts
.wd_end: .wd_end:

2
firmware/target/coldfire/iaudio/system-iaudio.c
View file

@ -71,7 +71,7 @@ void cf_set_cpu_frequency(long frequency)
RECALC_DELAYS(CPUFREQ_MAX); RECALC_DELAYS(CPUFREQ_MAX);
PLLCR = 0x0102c049 | (PLLCR & 0x70C00000); PLLCR = 0x0102c049 | (PLLCR & 0x70C00000);
CSCR0 = 0x00001180; /* Flash: 4 wait states */ CSCR0 = 0x00001180; /* Flash: 4 wait states */
CSCR1 = 0x00000980; /* LCD: 2 wait states */ CSCR1 = 0x00001180; /* LCD: 4 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
This may take up to 10ms! */ This may take up to 10ms! */
timers_adjust_prescale(CPUFREQ_MAX_MULT, true); timers_adjust_prescale(CPUFREQ_MAX_MULT, true);

4
firmware/target/coldfire/iriver/h100/adc-h100.c
View file

@ -37,7 +37,7 @@
({ \ ({ \
int _x_; \ int _x_; \
asm volatile ( \ asm volatile ( \
"move.l #11, %[_x_] \r\n" \ "move.l #13, %[_x_] \r\n" \
"1: \r\n" \ "1: \r\n" \
"subq.l #1, %[_x_] \r\n" \ "subq.l #1, %[_x_] \r\n" \
"bhi.b 1b \r\n" \ "bhi.b 1b \r\n" \
@ -94,7 +94,7 @@ unsigned short adc_scan(int channel)
data <<= 1; data <<= 1;
data |= DO?1:0; data |= DO?1:0;
} }
CS_HI; CS_HI;
set_irq_level(level); set_irq_level(level);

12
firmware/target/coldfire/iriver/h100/lcd-as-h100.S
View file

@ -29,8 +29,8 @@
lcd_write_command: lcd_write_command:
move.l (4,%sp),%d0 move.l (4,%sp),%d0
lea MBAR2,%a1 lea MBAR2,%a1
move.l #~8,%d1 move.l #~8,%d1
and.l %d1,(0xb4,%a1) and.l %d1,(0xb4,%a1)
move.w %d0,0xf0000000 move.w %d0,0xf0000000
rts rts
@ -77,19 +77,19 @@ lcd_write_command_ex:
lcd_write_data: lcd_write_data:
move.l (4,%sp),%a0 /* Data pointer */ move.l (4,%sp),%a0 /* Data pointer */
move.l (8,%sp),%d0 /* Length */ move.l (8,%sp),%d0 /* Length */
lea MBAR2,%a1 lea MBAR2,%a1
moveq #8,%d1 moveq #8,%d1
or.l %d1,(0xb4,%a1) or.l %d1,(0xb4,%a1)
lea 0xf0000000,%a1 lea 0xf0000000,%a1
.loop: .loop:
/* When running in IRAM, this loop takes 7 cycles plus the LCD write. /* When running in IRAM, this loop takes 10 cycles plus the LCD write.
The 7 cycles are necessary to follow the LCD timing specs The 10 cycles are necessary to follow the LCD timing specs
at 140MHz */ at 140MHz */
nop /* 3(0/0) */
move.b (%a0)+,%d1 /* 3(1/0) */ move.b (%a0)+,%d1 /* 3(1/0) */
move.w %d1,(%a1) /* 1(0/1) */ move.w %d1,(%a1) /* 1(0/1) */
subq.l #1,%d0 /* 1(0/0) */ subq.l #1,%d0 /* 1(0/0) */
nop /* 1(0/0) */
bne .loop /* 2(0/0) */ bne .loop /* 2(0/0) */
rts rts
.wd_end: .wd_end:

2
firmware/target/coldfire/pcf50606-coldfire.c
View file

@ -81,7 +81,7 @@ static int i2c_delay IDATA_ATTR = 44;
void pcf50606_i2c_recalc_delay(int cpu_clock) void pcf50606_i2c_recalc_delay(int cpu_clock)
{ {
i2c_delay = MAX(cpu_clock / (400000*2*3) - 7, 1); i2c_delay = MAX(cpu_clock / (400000*2*3) - 5, 1);
} }
inline void pcf50606_i2c_start(void) inline void pcf50606_i2c_start(void)

2
firmware/target/coldfire/system-target.h
View file

@ -155,7 +155,7 @@ static inline void invalidate_icache(void)
{ {
asm volatile ("move.l #0x01000000,%d0\n" asm volatile ("move.l #0x01000000,%d0\n"
"movec.l %d0,%cacr\n" "movec.l %d0,%cacr\n"
"move.l #0x80000000,%d0\n" "move.l #0x80000100,%d0\n"
"movec.l %d0,%cacr"); "movec.l %d0,%cacr");
} }