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[bugfix] x1000: Wait for FIFO to be empty rather than flushing

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When data is not in packed-16-bit mode, flushing the fifo
may result in swapping left and right channels if there
happens to be an odd number of entries in the FIFO.
This is especially likely when switching sample frequencies
for some reason.

When stopping PCM DMA, disable DMA and Underrun Interrupts
and then wait for FIFO to be empty before stopping AIC's playback.

Change-Id: I45b6b022c9e3889627842663cd9b7d2e0affb7c6
This commit is contained in:
Dana Conrad 2023-03-18 14:09:49 -05:00
parent 287747591e
commit b31127db7d
1 changed files with 17 additions and 2 deletions
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19
firmware/target/mips/ingenic_x1000/pcm-x1000.c
View file

@ -168,8 +168,23 @@ void pcm_play_dma_start(const void* addr, size_t size)
void pcm_play_dma_stop(void)
{
jz_writef(AIC_CCR, TDMS(0), ETUR(0), ERPL(0));
jz_writef(AIC_CCR, TFLUSH(1));
/* disable DMA and underrun interrupts */
jz_writef(AIC_CCR, TDMS(0), ETUR(0));
/*
* wait for FIFO to be empty - on targets
* with >16bit samples, flushing the fifo
* may result in swapping l and r channels!
* (ensure bit clock is running first)
*/
if (jz_readf(AIC_I2SCR, STPBK) == 0) {
while(jz_readf(AIC_SR, TFL) != 0);
} else {
panicf("pcm_play_dma_stop: No bit clock running!");
}
/* disable playback */
jz_writef(AIC_CCR, ERPL(0));
play_dma_pending_event = DMA_EVENT_NONE;
aic_state &= ~AIC_STATE_PLAYING;