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https://github.com/Rockbox/rockbox.git
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rk27xx: Turn off i2c clock when not in use
Change-Id: Ifc6c25a53ace1a5f4d716a33d4979ea0a37fac98
This commit is contained in:
Marcin Bukat
parent
16335da1cf
commit
ae27c331e1
1 changed files with 147 additions and 128 deletions
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@ -40,7 +40,7 @@ static struct mutex i2c_mtx;
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static bool i2c_write_byte(uint8_t data, bool start)
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{
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long timeout = current_tick + 50;
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long timeout = current_tick + HZ/50;
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/* START */
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I2C_CONR |= (1<<3) | (1<<2); /* master port enable, transmit bit */
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@ -66,34 +66,34 @@ static bool i2c_write_byte(uint8_t data, bool start)
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static bool i2c_read_byte(unsigned char *data)
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{
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long timeout = current_tick + HZ / 50;
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long timeout = current_tick + HZ/50;
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I2C_LCMR = (1<<2); /* resume op */
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I2C_LCMR = (1<<2); /* resume op */
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while (!(I2C_ISR & (1<<1)))
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if (TIME_AFTER(current_tick, timeout))
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return false;
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while (!(I2C_ISR & (1<<1)))
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if (TIME_AFTER(current_tick, timeout))
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return false;
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*data = I2C_MRXR;
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*data = I2C_MRXR;
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/* clear status bit */
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I2C_ISR &= ~(1<<1);
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/* clear status bit */
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I2C_ISR &= ~(1<<1);
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return true;
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return true;
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}
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static bool i2c_stop(void)
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{
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long timeout = current_tick + HZ / 50;
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long timeout = current_tick + HZ/50;
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I2C_CONR &= ~(1<<4);
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I2C_LCMR |= (1<<2) | (1<<1); /* resume op, stop */
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I2C_CONR &= ~(1<<4);
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I2C_LCMR |= (1<<2) | (1<<1); /* resume op, stop */
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while (I2C_LCMR & (1<<1))
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if (TIME_AFTER(current_tick, timeout))
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return false;
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while (I2C_LCMR & (1<<1))
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if (TIME_AFTER(current_tick, timeout))
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return false;
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return true;
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return true;
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}
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/* route i2c bus to internal codec or external bus
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@ -103,154 +103,173 @@ static bool i2c_stop(void)
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*/
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static void i2c_iomux(unsigned char slave)
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{
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unsigned long muxa = SCU_IOMUXA_CON & ~(0x1f<<14);
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unsigned long muxa = SCU_IOMUXA_CON & ~(0x1f<<14);
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if ((slave & 0xfe) == (0x27<<1))
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{
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/* internal codec */
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SCU_IOMUXA_CON = (muxa | (1<<16) | (1<<14));
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}
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else
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{
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/* external I2C bus */
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SCU_IOMUXA_CON = (muxa | (1<<18));
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}
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if ((slave & 0xfe) == (0x27<<1))
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{
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/* internal codec */
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SCU_IOMUXA_CON = (muxa | (1<<16) | (1<<14));
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}
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else
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{
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/* external I2C bus */
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SCU_IOMUXA_CON = (muxa | (1<<18));
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}
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}
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void i2c_init(void)
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{
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mutex_init(&i2c_mtx);
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mutex_init(&i2c_mtx);
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SCU_CLKCFG &= ~(1<< 20);
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I2C_OPR |= (1<<7); /* reset state machine */
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sleep(HZ/100);
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I2C_OPR &= ~((1<<7) | (1<<6)); /* clear ENABLE bit, deasert reset */
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/* ungate i2c module clock */
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SCU_CLKCFG &= ~(1<< 20);
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/* set I2C divider to stay within allowed SCL freq limit
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* APBfreq = 50Mhz
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* SCLfreq = (APBfreq/5*(I2CCDVR[5:3] + 1) * 2^((I2CCDVR[2:0] + 1))
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*/
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I2C_OPR |= (1<<7); /* reset state machine */
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sleep(HZ/100);
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I2C_OPR &= ~((1<<7) | (1<<6)); /* clear ENABLE bit, deasert reset */
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/* we are driving this slightly above specs
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* (6<<3) | (1<<0) 416kHz
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* (7<<3) | (1<<0) 357kHz
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* (6<<3) | (2<<0) 208kHz
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*/
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I2C_OPR = (I2C_OPR & ~(0x3F)) | (6<<3) | (1<<0);
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/* set I2C divider to stay within allowed SCL freq limit
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* APBfreq = 50Mhz
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* SCLfreq = (APBfreq/5*(I2CCDVR[5:3] + 1) * 2^((I2CCDVR[2:0] + 1))
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*/
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I2C_IER = 0x00;
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/* we are driving this slightly above specs
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* (6<<3) | (1<<0) 416kHz
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* (7<<3) | (1<<0) 357kHz
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* (6<<3) | (2<<0) 208kHz
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*/
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I2C_OPR = (I2C_OPR & ~(0x3F)) | (6<<3) | (1<<0);
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I2C_OPR |= (1<<6); /* enable i2c core */
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I2C_IER = 0x00;
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I2C_OPR |= (1<<6); /* enable i2c core */
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/* turn off i2c module clock until we need to comunicate */
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SCU_CLKCFG |= (1<< 20);
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}
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int i2c_write(unsigned char slave, int address, int len,
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const unsigned char *data)
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{
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mutex_lock(&i2c_mtx);
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int ret = 0;
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i2c_iomux(slave);
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mutex_lock(&i2c_mtx);
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/* clear all flags */
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I2C_ISR = 0x00;
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I2C_IER = 0x00;
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i2c_iomux(slave);
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/* START */
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if (! i2c_write_byte(slave & ~1, true))
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{
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mutex_unlock(&i2c_mtx);
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return 1;
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}
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/* ungate i2c clock */
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SCU_CLKCFG &= ~(1<<20);
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if (address >= 0)
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{
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if (! i2c_write_byte(address, false))
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{
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mutex_unlock(&i2c_mtx);
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return 2;
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}
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}
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/* clear all flags */
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I2C_ISR = 0x00;
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I2C_IER = 0x00;
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/* write data */
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while (len--)
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{
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if (! i2c_write_byte(*data++, false))
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{
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mutex_unlock(&i2c_mtx);
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return 4;
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}
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}
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/* START */
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if (! i2c_write_byte(slave & ~1, true))
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{
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ret = 1;
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goto end;
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}
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/* STOP */
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if (! i2c_stop())
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{
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mutex_unlock(&i2c_mtx);
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return 5;
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}
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if (address >= 0)
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{
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if (! i2c_write_byte(address, false))
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{
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ret = 2;
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goto end;
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}
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}
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mutex_unlock(&i2c_mtx);
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return 0;
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/* write data */
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while (len--)
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{
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if (! i2c_write_byte(*data++, false))
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{
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ret = 4;
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goto end;
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}
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}
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/* STOP */
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if (! i2c_stop())
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{
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ret = 5;
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goto end;
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}
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end:
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mutex_unlock(&i2c_mtx);
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SCU_CLKCFG |= (1<<20);
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return ret;
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}
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int i2c_read(unsigned char slave, int address, int len, unsigned char *data)
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{
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mutex_lock(&i2c_mtx);
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int ret = 0;
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i2c_iomux(slave);
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mutex_lock(&i2c_mtx);
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/* clear all flags */
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I2C_ISR = 0x00;
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I2C_IER = 0x00;
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i2c_iomux(slave);
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if (address >= 0)
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{
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/* START */
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if (! i2c_write_byte(slave & ~1, true))
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{
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mutex_unlock(&i2c_mtx);
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return 1;
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}
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/* ungate i2c module clock */
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SCU_CLKCFG &= ~(1<<20);
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/* write address */
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if (! i2c_write_byte(address, false))
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{
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mutex_unlock(&i2c_mtx);
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return 2;
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}
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}
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/* clear all flags */
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I2C_ISR = 0x00;
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I2C_IER = 0x00;
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/* (repeated) START */
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if (! i2c_write_byte(slave | 1, true))
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{
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mutex_unlock(&i2c_mtx);
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return 3;
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}
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if (address >= 0)
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{
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/* START */
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if (! i2c_write_byte(slave & ~1, true))
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{
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ret = 1;
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goto end;
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}
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I2C_CONR &= ~(1<<3); /* clear transmit bit (switch to receive mode) */
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/* write address */
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if (! i2c_write_byte(address, false))
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{
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ret = 2;
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goto end;
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}
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}
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while (len)
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{
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if (! i2c_read_byte(data++))
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{
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mutex_unlock(&i2c_mtx);
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return 4;
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}
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/* (repeated) START */
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if (! i2c_write_byte(slave | 1, true))
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{
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ret = 3;
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goto end;
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}
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if (len == 1)
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I2C_CONR |= (1<<4); /* NACK */
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else
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I2C_CONR &= ~(1<<4); /* ACK */
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I2C_CONR &= ~(1<<3); /* clear transmit bit (switch to receive mode) */
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len--;
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}
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while (len)
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{
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if (! i2c_read_byte(data++))
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{
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ret = 4;
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goto end;
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}
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if (len == 1)
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I2C_CONR |= (1<<4); /* NACK */
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else
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I2C_CONR &= ~(1<<4); /* ACK */
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len--;
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}
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/* STOP */
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if (! i2c_stop())
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{
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mutex_unlock(&i2c_mtx);
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return 5;
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}
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if (! i2c_stop())
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{
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ret = 5;
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goto end;
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}
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mutex_unlock(&i2c_mtx);
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return 0;
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end:
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mutex_unlock(&i2c_mtx);
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SCU_CLKCFG |= (1<<20);
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return ret;
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}
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