diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c
index 16c89b9a7a..4bf5cd39c3 100644
--- a/firmware/target/arm/as3525/system-as3525.c
+++ b/firmware/target/arm/as3525/system-as3525.c
@@ -233,26 +233,6 @@ static void sdram_init(void)
 
     MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */
 }
-#else   /* !BOOTLOADER */
-void memory_init(void)
-{
-    ttb_init();
-    /* map every region to itself, uncached */
-    map_section(0, 0, 4096, CACHE_NONE);
-
-    /* IRAM */
-    map_section(0, IRAM_ORIG, 1, CACHE_ALL);
-    map_section(0, UNCACHED_ADDR(IRAM_ORIG), 1, CACHE_NONE);
-
-    /* DRAM */
-    map_section(0x30000000, DRAM_ORIG, MEMORYSIZE, CACHE_ALL);
-    map_section(0x30000000, UNCACHED_ADDR(DRAM_ORIG), MEMORYSIZE, CACHE_NONE);
-
-    /* map 1st mbyte of DRAM at 0x0 to have exception vectors available */
-    map_section(0x30000000, 0, 1, CACHE_ALL);
-
-    enable_mmu();
-}
 #endif /* BOOTLOADER */
 
 void system_init(void)
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S
index 5e65738d9c..5d07d34c59 100644
--- a/firmware/target/arm/crt0.S
+++ b/firmware/target/arm/crt0.S
@@ -58,9 +58,54 @@ newstart:
     msr     cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
 
 #if (CONFIG_CPU==AS3525 || CONFIG_CPU==AS3525v2) && !defined(BOOTLOADER)
+
+#define CACHE_NONE  0
+#define CACHE_ALL   0x0C
+#define UNCACHED_ADDR(a) (a + 0x10000000)
+
     /* Setup MMU : has to be done before accessing IRAM ! */
-    ldr     sp, =stackend
-    bl      memory_init
+
+    bl      ttb_init
+
+    mov     r0, #0                          @ physical address
+    mov     r1, #0                          @ virtual address
+    mov     r2, #0x1000                     @ size (all memory)
+    mov     r3, #CACHE_NONE
+    bl      map_section
+
+    mov     r0, #0                          @ physical address
+    mov     r1, #IRAM_ORIG                  @ virtual address
+    mov     r2, #1                          @ size : 1MB
+    mov     r3, #CACHE_ALL
+    bl      map_section
+
+    mov     r0, #0                          @ physical address
+    ldr     r1, =UNCACHED_ADDR(IRAM_ORIG)   @ virtual address
+    mov     r2, #1                          @ size : 1MB
+    mov     r3, #CACHE_NONE
+    bl      map_section
+
+    mov     r0, #0x30000000                 @ physical address
+    mov     r1, #DRAM_ORIG                  @ virtual address
+    mov     r2, #MEMORYSIZE                 @ size
+    mov     r3, #CACHE_ALL
+    bl      map_section
+
+    mov     r0, #0x30000000                 @ physical address
+    mov     r1, #UNCACHED_ADDR(DRAM_ORIG)   @ virtual address
+    mov     r2, #MEMORYSIZE                 @ size
+    mov     r3, #CACHE_NONE
+    bl      map_section
+
+    /* map 1st mbyte of DRAM at 0x0 to have exception vectors available */
+
+    mov     r0, #0x30000000                 @ physical address
+    mov     r1, #0                          @ virtual address
+    mov     r2, #1                          @ size
+    mov     r3, #CACHE_ALL
+    bl      map_section
+
+    bl      enable_mmu
 
     /* Zero out IBSS */
     ldr     r2, =_iedata