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iPod Nano 2G: Post-mortem memory dumper stub (FS#11701)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28573 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann
parent
e872e9b913
commit
a961798c2c
3 changed files with 312 additions and 0 deletions
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@ -1496,6 +1496,7 @@ target/arm/s5l8700/udacodec-meizu.c
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#ifdef IPOD_NANO2G
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#ifndef SIMULATOR
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target/arm/ipod/button-clickwheel.c
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target/arm/s5l8700/postmortemstub.S
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target/arm/s5l8700/kernel-s5l8700.c
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target/arm/s5l8700/dma-s5l8700.c
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target/arm/s5l8700/ipodnano2g/backlight-nano2g.c
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308
firmware/target/arm/s5l8700/postmortemstub.S
Executable file
308
firmware/target/arm/s5l8700/postmortemstub.S
Executable file
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@ -0,0 +1,308 @@
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.section .text.post_mortem_stub, "ax", %progbits
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.align 4
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.global post_mortem_stub
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.type post_mortem_stub, %function
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post_mortem_stub:
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MSR CPSR_c, #0xD3 @ Supervisor mode, no IRQs, no FIQs
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MRC p15, 0, R0,c1,c0
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BIC R0, R0, #5
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MCR p15, 0, R0,c1,c0 @ Disable the Protection Unit and DCache
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MOV R13, #0
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pms_flushcache_loop:
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MCR p15, 0, R13,c7,c14,2
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ADD R0, R13, #0x10
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MCR p15, 0, R0,c7,c14,2
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ADD R0, R0, #0x10
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MCR p15, 0, R0,c7,c14,2
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ADD R0, R0, #0x10
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MCR p15, 0, R0,c7,c14,2
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ADDS R13, R13, #0x04000000
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BNE pms_flushcache_loop
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MCR p15, 0, R13,c7,c10,4
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LDR R7, pms_00080200
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ORR R8, R7, #0x8000
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ADR R9, pms_recvbuf
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LDR R10, pms_20080040
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MOV R11, #0x38800000
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MOV R12, #1
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MOV R2, #0x3C400000
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ADD R1, R2, #0x00100000 @ Enable USB clocks
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LDR R0, [R1,#0x28]
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BIC R0, R0, #0x4000
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STR R0, [R1,#0x28]
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LDR R0, [R1,#0x40]
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BIC R0, R0, #0x800
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STR R0, [R1,#0x40]
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LDR R0, pms_20803180 @ Clocking config
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STR R0, [R1]
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MOV R0, #0x280
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STR R0, [R1,#0x3C]
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MRC p15, 0, R0,c1,c0
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ORR R0, R0, #0xc0000000
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MCR p15, 0, R0,c1,c0 @ Asynchronous mode
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STR R13, [R11,#0xE00] @ PHY clock enable
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MOV R1, #0x800
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ORR R0, R2, #2
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STR R0, [R11,#0x804] @ USB2 Gadget: Soft disconnect
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STR R13, [R2] @ USB2 PHY: Power on
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STR R12, [R2,#0x08] @ USB2 PHY: Assert Software Reset
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MOV R0, #0x10000
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pms_wait:
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SUBS R0, R0, #1
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BNE pms_wait
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STR R13, [R2,#0x08] @ USB2 PHY: Deassert Software Reset
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STR R13, [R2,#0x04] @ USB2 PHY: Clock is 48MHz
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STR R12, [R11,#0x10] @ USB2 Gadget: Assert Core Software Reset
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pms_waitcorereset:
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LDR R0, [R11,#0x10] @ USB2 Gadget: Wait for Core to reset
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TST R0, #1
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BNE pms_waitcorereset
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TST R0, #0x80000000 @ USB2 Gadget: Wait for AHB IDLE
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BEQ pms_waitcorereset
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MOV R0, #0x200
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STR R0, [R11,#0x24] @ USB2 Gadget: RX FIFO size: 512 bytes
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ORR R0, R0, #0x2000000
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STR R0, [R11,#0x28] @ USB2 Gadget: Non-periodic TX FIFO size: 512 bytes
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MOV R0, #0x26
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STR R0, [R11,#0x08] @ USB2 Gadget: DMA Enable, Burst Length: 4, Mask Interrupts
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MOV R0, #0x1400
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ADD R0, R0, #8
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STR R0, [R11,#0x0C] @ USB2 Gadget: PHY IF is 16bit, Turnaround 5
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STR R1, [R11,#0x804] @ USB2 Gadget: Soft reconnect
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ADR R14, pms_ctrlbuf
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ORR R5, R8, #0x84000000
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@ fallthrough
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pms_mainloop:
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LDR R3, [R11,#0x14] @ Global USB interrupts
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TST R3, #0x00001000 @ BUS reset
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BEQ pms_noreset
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MOV R0, #0x500
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STR R0, [R11,#0x804]
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MOV R0, #4
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STR R0, [R11,#0x800] @ USB2 Gadget: Device Address 0, STALL on non-zero length status stage
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MOV R0, #0x8000
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STR R0, [R11,#0x900] @ USB2 Gadget: Endpoint 0 IN Control: ACTIVE
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STR R10, [R11,#0xB10] @ USB2 Gadget: Endpoint 0 OUT Transfer Size: 64 Bytes, 1 Packet, 1 Setup Packet
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STR R14, [R11,#0xB14] @ USB2 Gadget: Endpoint 0 OUT DMA Address: pms_ctrlbuf
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ORR R6, R0, #0x84000000
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STR R6, [R11,#0xB00] @ USB2 Gadget: Endpoint 0 OUT Control: ENABLE CLEARNAK
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STR R8, [R11,#0x960] @ USB2 Gadget: Endpoint 3 IN Control: ACTIVE BULK, 512 byte packets
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STR R8, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ACTIVE BULK, 512 byte packets
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STR R7, [R11,#0xB90] @ USB2 Gadget: Endpoint 4 OUT Transfer Size: 512 Bytes, 1 Packet
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STR R9, [R11,#0xB94] @ USB2 Gadget: Endpoint 4 OUT DMA Address: pms_recvbuf
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ORR R4, R5, #0x10000000
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STR R4, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ENABLE CLEARNAK DATA0
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pms_noreset:
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LDR R0, [R11,#0x908] @ Just ACK all IN events...
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STR R0, [R11,#0x908]
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LDR R0, [R11,#0x968]
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STR R0, [R11,#0x968]
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LDR R2, [R11,#0xB08]
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MOVS R2, R2 @ Event on OUT EP0
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BEQ pms_noep0out
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TST R2, #8 @ SETUP phase done
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BEQ pms_controldone
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LDRB R0, [R14,#1] @ Get request type
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CMP R0, #0
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BEQ pms_GET_STATUS
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CMP R0, #1
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BEQ pms_CLEAR_FEATURE
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CMP R0, #3
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BEQ pms_SET_FEATURE
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CMP R0, #5
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BEQ pms_SET_ADDRESS
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CMP R0, #6
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BEQ pms_GET_DESCRIPTOR
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CMP R0, #8
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BEQ pms_GET_CONFIGURATION
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CMP R0, #9
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BEQ pms_SET_CONFIGURATION
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pms_ctrlstall:
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LDR R0, [R11,#0x900]
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ORR R0, R0, #0x00200000
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STR R0, [R11,#0x900] @ Stall IN EP0
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LDR R0, [R11,#0xB00]
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ORR R0, R0, #0x00200000
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STR R0, [R11,#0xB00] @ Stall OUT EP0
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pms_controldone:
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STR R10, [R11,#0xB10] @ OUT EP0: 64 Bytes, 1 Packet, 1 Setup Packet
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STR R14, [R11,#0xB14] @ OUT EP0: DMA address
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STR R6, [R11,#0xB00] @ OUT EP0: Enable ClearNAK
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pms_noep0out:
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STR R2, [R11,#0xB08] @ ACK it, whatever it was...
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LDR R2, [R11,#0xB88]
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MOVS R2, R2 @ Event on OUT EP4
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BEQ pms_noep1out
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TST R2, #1 @ XFER complete
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BEQ pms_datadone
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LDR R0, pms_000001FF
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LDR R1, pms_recvbuf+4
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ADD R0, R0, R1
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MOV R0, R0,LSR#9
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ORR R1, R1, R0,LSL#19 @ Number of packets
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LDR R0, pms_recvbuf
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STR R1, [R11,#0x970] @ EP3 IN: Number of packets, size
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STR R0, [R11,#0x974] @ EP3 IN: DMA address
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STR R5, [R11,#0x960] @ EP3 IN: Enable ClearNAK
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pms_datadone:
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STR R7, [R11,#0xB90] @ OUT EP4: 512 Bytes, 1 Packet
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STR R9, [R11,#0xB94] @ Out EP4: DMA address
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STR R5, [R11,#0xB80] @ Out EP4: Enable ClearNAK
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pms_noep1out:
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STR R2, [R11,#0xB88] @ ACK it, whatever it was...
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STR R3, [R11,#0x14] @ ACK global ints
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B pms_mainloop
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pms_CLEAR_FEATURE:
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LDRB R0, [R14]
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CMP R0, #2
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LDREQ R0, [R14,#2]
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BICEQ R0, R0, #0x00800000
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CMPEQ R0, #0x00010000
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@ fallthrough
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pms_SET_CONFIGURATION:
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ORREQ R0, R8, #0x10000000
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STREQ R0, [R11,#0x960] @ EP3 IN: Set DATA0 PID
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STREQ R4, [R11,#0xB80] @ EP4 OUT: Set DATA0 PID
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B pms_SET_FEATURE @ zero-length ACK
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pms_GET_CONFIGURATION:
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MOV R1, #1
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STR R1, [R14]
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@ fallthrough
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pms_ctrlsend:
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ORR R0, R1, #0x00080000 @ 1 Packet
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STR R0, [R11,#0x910] @ EP0 IN: 1 Packet, Size as in R1
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STR R14, [R11,#0x914] @ EP0 IN: DMA address
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ORR R0, R6, #0x1800
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STR R0, [R11,#0x900] @ EP0 IN: Enable ClearNAK
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ADR R14, pms_ctrlbuf
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B pms_controldone
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pms_GET_DESCRIPTOR:
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LDRB R0, [R14,#3] @ Descriptor type
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CMP R0, #1
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ADREQ R14, pms_devicedescriptor
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BEQ pms_senddescriptor
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CMP R0, #2
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ADREQ R14, pms_configurationdescriptor
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MOVEQ R1, #0x20
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BEQ pms_senddescriptorcustomsize
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CMP R0, #3
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BNE pms_ctrlstall
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LDRB R0, [R14,#2] @ String descriptor index
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CMP R0, #0
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LDREQ R0, pms_langstringdescriptor
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STREQ R0, [R14]
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BEQ pms_senddescriptor
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CMP R0, #1
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CMPNE R0, #2
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ADREQ R14, pms_devnamestringdescriptor
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BNE pms_ctrlstall
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@ fallthrough
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pms_senddescriptor:
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LDRB R1, [R14] @ Descriptor length
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@ fallthrough
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pms_senddescriptorcustomsize:
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LDRH R0, pms_ctrlbuf+6 @ Requested length
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CMP R0, R1
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MOVLO R1, R0
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B pms_ctrlsend
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pms_SET_ADDRESS:
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LDRH R1, [R14,#2] @ new address
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LDR R0, [R11,#0x800]
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BIC R0, R0, #0x000007F0
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ORR R0, R0, R1,LSL#4
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STR R0, [R11,#0x800] @ set new address
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@ fallthrough
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pms_SET_FEATURE:
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MOV R1, #0 @ zero-length ACK
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B pms_ctrlsend
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pms_20803180:
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.word 0x20803180
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.ltorg
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.align 4
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pms_configurationdescriptor:
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.word 0x00200209
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.word 0xC0000101
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.word 0x00040932
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.word 0xFFFF0200
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.word 0x050700FF
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.word 0x02000204
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.word 0x83050701
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.word 0x01020002
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pms_devicedescriptor:
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.word 0x02000112
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.word 0x40FFFFFF
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.word 0xA112FFFF
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.word 0x02010001
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.word 0x00010100
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pms_00080200:
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.word 0x00080200
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pms_20080040:
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.word 0x20080040
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pms_000001FF:
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.word 0x000001FF
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pms_devnamestringdescriptor:
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.word 0x0052030C
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.word 0x00500042
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.word 0x0053004D
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pms_langstringdescriptor:
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.word 0x04090304
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pms_ctrlbuf:
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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pms_recvbuf:
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.word 0
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.word 0
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pms_GET_STATUS:
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LDRB R0, [R14]
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CMP R0, #0x80
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STREQ R12, [R14]
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STRNE R13, [R14]
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MOV R1, #2
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B pms_ctrlsend
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.size post_mortem_stub, .-post_mortem_stub
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@ -182,8 +182,11 @@ void system_reboot(void)
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#endif
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}
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extern void post_mortem_stub(void);
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void system_exception_wait(void)
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{
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post_mortem_stub();
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while(1);
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}
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