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Make storage alignement use cache alignement macros

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Introduce STORAGE_ALIGN_DOWN, STORAGE_PAD (using new CACHE_PAD) and
STORAGE_OVERLAP (using new CACHE_OVERLAP), make them useful only when
PROC_NEEDS_CACHEALIGN and STORAGE_NEEDS_ALIGN are defined

Modify PP and nano2g system-target.h accordingly

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25336 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2010-03-25 23:01:56 +00:00
parent 43bc2e586a
commit a8d1690ffe
6 changed files with 33 additions and 25 deletions
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5
firmware/target/arm/s5l8700/system-target.h
View file

@ -29,6 +29,11 @@
#define CPUFREQ_NORMAL 47923200
#define CPUFREQ_MAX 191692800
/* DMA engine needs aligned addresses */
#define PROC_NEEDS_CACHEALIGN
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#define NEEDS_STORAGE_ALIGN
#define inl(a) (*(volatile unsigned long *) (a))
#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
#define inb(a) (*(volatile unsigned char *) (a))

5
firmware/target/arm/system-target.h
View file

@ -22,6 +22,7 @@
#ifndef SYSTEM_TARGET_H
#define SYSTEM_TARGET_H
#include "config.h"
#include "system-arm.h"
#ifdef CPU_PP
@ -162,6 +163,10 @@ static inline void wake_core(int core)
#define PROC_NEEDS_CACHEALIGN
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#if defined(CPU_PP502x) && defined(HAVE_ATA_DMA)
#define NEEDS_STORAGE_ALIGN
#endif
/** cache functions **/
#ifndef BOOTLOADER
#define HAVE_CPUCACHE_INVALIDATE