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imx233: rewrite ssp using new register headers
Change-Id: Ibf186b610beb07bd615c976630cdca9de2c7448e
This commit is contained in:
Amaury Pouly
parent
94cb72301d
commit
a759242b55
3 changed files with 73 additions and 151 deletions
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@ -287,7 +287,7 @@ static int init_sd_card(int drive)
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sdmmc_power(drive, true);
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imx233_ssp_start(ssp);
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imx233_ssp_softreset(ssp);
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imx233_ssp_set_mode(ssp, HW_SSP_CTRL1__SSP_MODE__SD_MMC);
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imx233_ssp_set_mode(ssp, BV_SSP_CTRL1_SSP_MODE__SD_MMC);
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/* SSPCLK @ 96MHz
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* gives bitrate of 96000 / 240 / 1 = 400kHz */
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imx233_ssp_set_timings(ssp, 240, 0, 0xffff);
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@ -397,7 +397,7 @@ static int init_mmc_drive(int drive)
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sdmmc_power(drive, true);
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imx233_ssp_start(ssp);
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imx233_ssp_softreset(ssp);
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imx233_ssp_set_mode(ssp, HW_SSP_CTRL1__SSP_MODE__SD_MMC);
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imx233_ssp_set_mode(ssp, BV_SSP_CTRL1_SSP_MODE__SD_MMC);
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/* SSPCLK @ 96MHz
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* gives bitrate of 96000 / 240 / 1 = 400kHz */
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imx233_ssp_set_timings(ssp, 240, 0, 0xffff);
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@ -29,9 +29,17 @@
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#if 0
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#define ASSERT_SSP(ssp) if(ssp < 1 || ssp > 2) panicf("ssp=%d in %s", ssp, __func__);
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#else
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#define ASSERT_SSP(ssp)
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#define ASSERT_SSP(ssp) (void) ssp;
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#endif
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/* Hack to handle both single and multi devices at once */
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#define SSP_SETn(reg, n, field) BF_SETn(reg, n, field)
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#define SSP_CLRn(reg, n, field) BF_CLRn(reg, n, field)
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#define SSP_RDn(reg, n, field) BF_RDn(reg, n, field)
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#define SSP_WRn(reg, n, field, val) BF_WRn(reg, n, field, val)
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#define SSP_WRn_V(reg, n, field, val) BF_WRn_V(reg, n, field, val)
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#define SSP_REGn(reg, n) HW_##reg(n)
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/* Used for DMA */
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struct ssp_dma_command_t
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{
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@ -46,15 +54,15 @@ struct ssp_dma_command_t
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__ENSURE_STRUCT_CACHE_FRIENDLY(struct ssp_dma_command_t)
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static bool ssp_in_use[2];
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static bool ssp_in_use[IMX233_NR_SSP];
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static int ssp_nr_in_use = 0;
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static struct mutex ssp_mutex[2];
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static struct semaphore ssp_sema[2];
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static struct ssp_dma_command_t ssp_dma_cmd[2];
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static uint32_t ssp_bus_width[2];
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static unsigned ssp_log_block_size[2];
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static ssp_detect_cb_t ssp_detect_cb[2];
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static bool ssp_detect_invert[2];
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static struct mutex ssp_mutex[IMX233_NR_SSP];
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static struct semaphore ssp_sema[IMX233_NR_SSP];
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static struct ssp_dma_command_t ssp_dma_cmd[IMX233_NR_SSP];
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static uint32_t ssp_bus_width[IMX233_NR_SSP];
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static unsigned ssp_log_block_size[IMX233_NR_SSP];
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static ssp_detect_cb_t ssp_detect_cb[IMX233_NR_SSP];
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static bool ssp_detect_invert[IMX233_NR_SSP];
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void INT_SSP(int ssp)
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{
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@ -88,16 +96,15 @@ void INT_SSP2_ERROR(void)
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void imx233_ssp_init(void)
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{
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/* power down */
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__REG_SET(HW_SSP_CTRL0(1)) = __BLOCK_CLKGATE;
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__REG_SET(HW_SSP_CTRL0(2)) = __BLOCK_CLKGATE;
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/* power down and init data structures */
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ssp_nr_in_use = 0;
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semaphore_init(&ssp_sema[0], 1, 0);
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semaphore_init(&ssp_sema[1], 1, 0);
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mutex_init(&ssp_mutex[0]);
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mutex_init(&ssp_mutex[1]);
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ssp_bus_width[0] = ssp_bus_width[1] = HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT;
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for(int i = 0; i < IMX233_NR_SSP; i++)
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{
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SSP_SETn(SSP_CTRL0, 1 + i, CLKGATE);
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semaphore_init(&ssp_sema[i], 1, 0);
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mutex_init(&ssp_mutex[i]);
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ssp_bus_width[i] = BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT;
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}
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}
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void imx233_ssp_start(int ssp)
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@ -107,7 +114,7 @@ void imx233_ssp_start(int ssp)
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return;
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ssp_in_use[ssp - 1] = true;
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/* Gate block */
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imx233_reset_block(&HW_SSP_CTRL0(ssp));
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imx233_reset_block(&SSP_REGn(SSP_CTRL0, ssp));
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/* Gate dma channel */
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imx233_dma_clkgate_channel(APB_SSP(ssp), true);
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/* If first block to start, start SSP clock */
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@ -132,7 +139,7 @@ void imx233_ssp_stop(int ssp)
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return;
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ssp_in_use[ssp - 1] = false;
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/* Gate off */
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__REG_SET(HW_SSP_CTRL0(ssp)) = __BLOCK_CLKGATE;
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SSP_SETn(SSP_CTRL0, ssp, CLKGATE);
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/* Gate off dma */
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imx233_dma_clkgate_channel(APB_SSP(ssp), false);
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/* If last block to stop, stop SSP clock */
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@ -153,8 +160,8 @@ void imx233_ssp_softreset(int ssp)
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void imx233_ssp_set_timings(int ssp, int divide, int rate, int timeout)
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{
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ASSERT_SSP(ssp)
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HW_SSP_TIMING(ssp) = divide << HW_SSP_TIMING__CLOCK_DIVIDE_BP | rate |
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timeout << HW_SSP_TIMING__CLOCK_TIMEOUT_BP;
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SSP_REGn(SSP_TIMING, ssp) = BF_OR3(SSP_TIMING, CLOCK_DIVIDE(divide),
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CLOCK_RATE(rate), TIMEOUT(timeout));
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}
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void imx233_ssp_setup_ssp1_sd_mmc_pins(bool enable_pullups, unsigned bus_width,
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@ -223,16 +230,15 @@ void imx233_ssp_setup_ssp2_sd_mmc_pins(bool enable_pullups, unsigned bus_width,
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void imx233_ssp_set_mode(int ssp, unsigned mode)
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{
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ASSERT_SSP(ssp)
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/* set mode */
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SSP_WRn(SSP_CTRL1, ssp, SSP_MODE, mode);
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/* set mode specific settings */
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switch(mode)
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{
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case HW_SSP_CTRL1__SSP_MODE__SD_MMC:
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/* clear mode and word length */
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__REG_CLR(HW_SSP_CTRL1(ssp)) =
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HW_SSP_CTRL1__SSP_MODE_BM | HW_SSP_CTRL1__WORD_LENGTH_BM;
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/* set mode, set word length to 8-bit, polarity and enable dma */
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__REG_SET(HW_SSP_CTRL1(ssp)) = mode |
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HW_SSP_CTRL1__WORD_LENGTH__EIGHT_BITS << HW_SSP_CTRL1__WORD_LENGTH_BP |
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HW_SSP_CTRL1__POLARITY | HW_SSP_CTRL1__DMA_ENABLE;
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case BV_SSP_CTRL1_SSP_MODE__SD_MMC:
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SSP_WRn_V(SSP_CTRL1, ssp, WORD_LENGTH, EIGHT_BITS);
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SSP_SETn(SSP_CTRL1, ssp, POLARITY);
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SSP_SETn(SSP_CTRL1, ssp, DMA_ENABLE);
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break;
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default: return;
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}
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@ -243,9 +249,9 @@ void imx233_ssp_set_bus_width(int ssp, unsigned width)
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ASSERT_SSP(ssp)
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switch(width)
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{
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case 1: ssp_bus_width[ssp - 1] = HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT; break;
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case 4: ssp_bus_width[ssp - 1] = HW_SSP_CTRL0__BUS_WIDTH__FOUR_BIT; break;
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case 8: ssp_bus_width[ssp - 1] = HW_SSP_CTRL0__BUS_WIDTH__EIGHT_BIT; break;
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case 1: ssp_bus_width[ssp - 1] = BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT; break;
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case 4: ssp_bus_width[ssp - 1] = BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT; break;
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case 8: ssp_bus_width[ssp - 1] = BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT; break;
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}
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}
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@ -267,19 +273,15 @@ enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
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unsigned xfer_size = block_count * (1 << ssp_log_block_size[ssp - 1]);
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ssp_dma_cmd[ssp - 1].cmd0 = cmd | HW_SSP_CMD0__APPEND_8CYC |
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ssp_log_block_size[ssp - 1] << HW_SSP_CMD0__BLOCK_SIZE_BP |
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(block_count - 1) << HW_SSP_CMD0__BLOCK_COUNT_BP;
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ssp_dma_cmd[ssp - 1].cmd0 = BF_OR4(SSP_CMD0, CMD(cmd), APPEND_8CYC(1),
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BLOCK_SIZE(ssp_log_block_size[ssp - 1]), BLOCK_COUNT(block_count - 1));
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ssp_dma_cmd[ssp - 1].cmd1 = cmd_arg;
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/* setup all flags and run */
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ssp_dma_cmd[ssp - 1].ctrl0 = xfer_size | HW_SSP_CTRL0__ENABLE |
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(buffer ? 0 : HW_SSP_CTRL0__IGNORE_CRC) |
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(wait4irq ? HW_SSP_CTRL0__WAIT_FOR_IRQ : 0) |
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(resp != SSP_NO_RESP ? HW_SSP_CTRL0__GET_RESP : 0) |
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(resp == SSP_LONG_RESP ? HW_SSP_CTRL0__LONG_RESP : 0) |
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(ssp_bus_width[ssp - 1] << HW_SSP_CTRL0__BUS_WIDTH_BP) |
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(buffer ? HW_SSP_CTRL0__DATA_XFER : 0) |
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(read ? HW_SSP_CTRL0__READ : 0);
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ssp_dma_cmd[ssp - 1].ctrl0 = BF_OR9(SSP_CTRL0, XFER_COUNT(xfer_size),
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ENABLE(1), IGNORE_CRC(buffer == NULL), WAIT_FOR_IRQ(wait4irq),
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GET_RESP(resp != SSP_NO_RESP), LONG_RESP(resp == SSP_LONG_RESP),
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BUS_WIDTH(ssp_bus_width[ssp - 1]), DATA_XFER(buffer != NULL),
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READ(read));
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/* setup the dma parameters */
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ssp_dma_cmd[ssp - 1].dma.buffer = buffer;
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ssp_dma_cmd[ssp - 1].dma.next = NULL;
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@ -291,7 +293,8 @@ enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
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(3 << HW_APB_CHx_CMD__CMDWORDS_BP) |
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(xfer_size << HW_APB_CHx_CMD__XFER_COUNT_BP);
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__REG_CLR(HW_SSP_CTRL1(ssp)) = HW_SSP_CTRL1__ALL_IRQ;
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SSP_CLRn(SSP_CTRL1, ssp, ALL_IRQ);
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imx233_dma_reset_channel(APB_SSP(ssp));
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imx233_dma_start_command(APB_SSP(ssp), &ssp_dma_cmd[ssp - 1].dma);
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@ -304,10 +307,9 @@ enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
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imx233_dma_reset_channel(APB_SSP(ssp));
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ret = SSP_TIMEOUT;
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}
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else if((HW_SSP_CTRL1(ssp) & HW_SSP_CTRL1__ALL_IRQ) == 0)
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else if((SSP_REGn(SSP_CTRL1, ssp) & BM_SSP_CTRL1_ALL_IRQ) == 0)
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ret = SSP_SUCCESS;
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else if(HW_SSP_CTRL1(ssp) & (HW_SSP_CTRL1__RESP_TIMEOUT_IRQ |
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HW_SSP_CTRL1__DATA_TIMEOUT_IRQ | HW_SSP_CTRL1__RECV_TIMEOUT_IRQ))
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else if((SSP_REGn(SSP_CTRL1, ssp) & BM_SSP_CTRL1_TIMEOUT_IRQ))
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ret = SSP_TIMEOUT;
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else
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ret = SSP_ERROR;
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@ -315,12 +317,12 @@ enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
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if(resp_ptr != NULL)
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{
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if(resp != SSP_NO_RESP)
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*resp_ptr++ = HW_SSP_SDRESP0(ssp);
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*resp_ptr++ = SSP_REGn(SSP_SDRESP0, ssp);
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if(resp == SSP_LONG_RESP)
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{
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*resp_ptr++ = HW_SSP_SDRESP1(ssp);
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*resp_ptr++ = HW_SSP_SDRESP2(ssp);
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*resp_ptr++ = HW_SSP_SDRESP3(ssp);
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*resp_ptr++ = SSP_REGn(SSP_SDRESP1, ssp);
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*resp_ptr++ = SSP_REGn(SSP_SDRESP2, ssp);
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*resp_ptr++ = SSP_REGn(SSP_SDRESP3, ssp);
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}
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}
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mutex_unlock(&ssp_mutex[ssp - 1]);
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@ -330,10 +332,10 @@ enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
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void imx233_ssp_sd_mmc_power_up_sequence(int ssp)
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{
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ASSERT_SSP(ssp)
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__REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__SLOW_CLKING_EN;
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__REG_SET(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN;
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SSP_CLRn(SSP_CMD0, ssp, SLOW_CLKING_EN);
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SSP_SETn(SSP_CMD0, ssp, CONT_CLKING_EN);
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mdelay(1);
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__REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN;
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SSP_CLRn(SSP_CMD0, ssp, CONT_CLKING_EN);
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}
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static int ssp_detect_oneshot_callback(int ssp)
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@ -395,7 +397,7 @@ bool imx233_ssp_sdmmc_is_detect_inverted(int ssp)
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bool imx233_ssp_sdmmc_detect_raw(int ssp)
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{
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ASSERT_SSP(ssp)
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return !!(HW_SSP_STATUS(ssp) & HW_SSP_STATUS__CARD_DETECT);
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return SSP_RDn(SSP_STATUS, ssp, CARD_DETECT);
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}
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bool imx233_ssp_sdmmc_detect(int ssp)
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@ -27,106 +27,26 @@
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#include "pinctrl-imx233.h"
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#include "dma-imx233.h"
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#include "regs/regs-ssp.h"
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#define IMX233_NR_SSP 2
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/* ssp can value 1 or 2 */
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#define __SSP_SELECT(ssp, ssp1, ssp2) ((ssp) == 1 ? (ssp1) : (ssp2))
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#define INT_SRC_SSP_DMA(ssp) __SSP_SELECT(ssp, INT_SRC_SSP1_DMA, INT_SRC_SSP2_DMA)
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#define INT_SRC_SSP_ERROR(ssp) __SSP_SELECT(ssp, INT_SRC_SSP1_ERROR, INT_SRC_SSP2_ERROR)
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#define HW_SSP1_BASE 0x80010000
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#define HW_SSP2_BASE 0x80034000
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#define BP_SSP_CTRL1_ALL_IRQ 0
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#define BM_SSP_CTRL1_ALL_IRQ \
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BM_OR8(SSP_CTRL1, SDIO_IRQ, RESP_ERR_IRQ, RESP_TIMEOUT_IRQ, DATA_TIMEOUT_IRQ, \
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DATA_CRC_IRQ, FIFO_UNDERRUN_IRQ, RECV_TIMEOUT_IRQ, FIFO_OVERRUN_IRQ)
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#define BM_SSP_CTRL1_ALL_IRQ_EN \
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BM_OR8(SSP_CTRL1, SDIO_IRQ_EN, RESP_ERR_IRQ_EN, RESP_TIMEOUT_IRQ_EN, DATA_TIMEOUT_IRQ_EN, \
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DATA_CRC_IRQ_EN, FIFO_UNDERRUN_EN, RECV_TIMEOUT_IRQ_EN, FIFO_OVERRUN_IRQ_EN)
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#define HW_SSP_BASE(ssp) __SSP_SELECT(ssp, HW_SSP1_BASE, HW_SSP2_BASE)
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#define HW_SSP_CTRL0(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x0))
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#define HW_SSP_CTRL0__RUN (1 << 29)
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#define HW_SSP_CTRL0__SDIO_IRQ_CHECK (1 << 28)
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#define HW_SSP_CTRL0__LOCK_CS (1 << 27)
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#define HW_SSP_CTRL0__IGNORE_CRC (1 << 26)
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#define HW_SSP_CTRL0__READ (1 << 25)
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#define HW_SSP_CTRL0__DATA_XFER (1 << 24)
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#define HW_SSP_CTRL0__BUS_WIDTH_BM (3 << 22)
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#define HW_SSP_CTRL0__BUS_WIDTH_BP 22
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#define HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT 0
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#define HW_SSP_CTRL0__BUS_WIDTH__FOUR_BIT 1
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#define HW_SSP_CTRL0__BUS_WIDTH__EIGHT_BIT 2
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#define HW_SSP_CTRL0__WAIT_FOR_IRQ (1 << 21)
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#define HW_SSP_CTRL0__WAIT_FOR_CMD (1 << 20)
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#define HW_SSP_CTRL0__LONG_RESP (1 << 19)
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#define HW_SSP_CTRL0__CHECK_RESP (1 << 18)
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#define HW_SSP_CTRL0__GET_RESP (1 << 17)
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#define HW_SSP_CTRL0__ENABLE (1 << 16)
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#define HW_SSP_CTRL0__XFER_COUNT_BM 0xffff
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#define HW_SSP_CMD0(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x10))
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#define HW_SSP_CMD0__SLOW_CLKING_EN (1 << 22)
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#define HW_SSP_CMD0__CONT_CLKING_EN (1 << 21)
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#define HW_SSP_CMD0__APPEND_8CYC (1 << 20)
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#define HW_SSP_CMD0__BLOCK_SIZE_BM (0xf << 16)
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#define HW_SSP_CMD0__BLOCK_SIZE_BP 16
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#define HW_SSP_CMD0__BLOCK_COUNT_BM (0xff << 8)
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#define HW_SSP_CMD0__BLOCK_COUNT_BP 8
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#define HW_SSP_CMD0__CMD_BM 0xff
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#define HW_SSP_CMD1(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x20))
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#define HW_SSP_TIMING(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x50))
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#define HW_SSP_TIMING__CLOCK_TIMEOUT_BM 0xffff0000
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#define HW_SSP_TIMING__CLOCK_TIMEOUT_BP 16
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#define HW_SSP_TIMING__CLOCK_DIVIDE_BM 0xff00
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#define HW_SSP_TIMING__CLOCK_DIVIDE_BP 8
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#define HW_SSP_TIMING__CLOCK_RATE_BM 0xff
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#define HW_SSP_CTRL1(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x60))
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#define HW_SSP_CTRL1__SDIO_IRQ (1 << 31)
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#define HW_SSP_CTRL1__SDIO_IRQ_EN (1 << 30)
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#define HW_SSP_CTRL1__RESP_ERR_IRQ (1 << 29)
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#define HW_SSP_CTRL1__RESP_ERR_IRQ_EN (1 << 28)
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#define HW_SSP_CTRL1__RESP_TIMEOUT_IRQ (1 << 27)
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#define HW_SSP_CTRL1__RESP_TIMEOUT_IRQ_EN (1 << 26)
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#define HW_SSP_CTRL1__DATA_TIMEOUT_IRQ (1 << 25)
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#define HW_SSP_CTRL1__DATA_TIMEOUT_IRQ_EN (1 << 24)
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#define HW_SSP_CTRL1__DATA_CRC_IRQ (1 << 23)
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#define HW_SSP_CTRL1__DATA_CRC_IRQ_EN (1 << 22)
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#define HW_SSP_CTRL1__FIFO_UNDERRUN_IRQ (1 << 21)
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#define HW_SSP_CTRL1__FIFO_UNDERRUN_IRQ_EN (1 << 20)
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#define HW_SSP_CTRL1__RECV_TIMEOUT_IRQ (1 << 17)
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#define HW_SSP_CTRL1__RECV_TIMEOUT_IRQ_EN (1 << 16)
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#define HW_SSP_CTRL1__FIFO_OVERRUN_IRQ (1 << 15)
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#define HW_SSP_CTRL1__FIFO_OVERRUN_IRQ_EN (1 << 14)
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#define HW_SSP_CTRL1__DMA_ENABLE (1 << 13)
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#define HW_SSP_CTRL1__SLAVE_OUT_DISABLE (1 << 11)
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#define HW_SSP_CTRL1__PHASE (1 << 10)
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#define HW_SSP_CTRL1__POLARITY (1 << 9)
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#define HW_SSP_CTRL1__SLAVE_MODE (1 << 8)
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#define HW_SSP_CTRL1__WORD_LENGTH_BM (0xf << 4)
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#define HW_SSP_CTRL1__WORD_LENGTH_BP 4
|
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#define HW_SSP_CTRL1__WORD_LENGTH__EIGHT_BITS 0x7
|
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#define HW_SSP_CTRL1__SSP_MODE_BM 0xf
|
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#define HW_SSP_CTRL1__SSP_MODE__SD_MMC 0x3
|
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#define HW_SSP_CTRL1__ALL_IRQ 0xaaa28000
|
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|
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#define HW_SSP_DATA(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x70))
|
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|
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#define HW_SSP_SDRESP0(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x80))
|
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#define HW_SSP_SDRESP1(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x90))
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#define HW_SSP_SDRESP2(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0xA0))
|
||||
#define HW_SSP_SDRESP3(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0xB0))
|
||||
|
||||
#define HW_SSP_STATUS(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0xC0))
|
||||
#define HW_SSP_STATUS__RECV_TIMEOUT_STAT (1 << 11)
|
||||
#define HW_SSP_STATUS__TIMEOUT (1 << 12)
|
||||
#define HW_SSP_STATUS__DATA_CRC_ERR (1 << 13)
|
||||
#define HW_SSP_STATUS__RESP_TIMEOUT (1 << 14)
|
||||
#define HW_SSP_STATUS__RESP_ERR (1 << 15)
|
||||
#define HW_SSP_STATUS__RESP_CRC_ERR (1 << 16)
|
||||
#define HW_SSP_STATUS__CARD_DETECT (1 << 28)
|
||||
#define HW_SSP_STATUS__ALL_ERRORS 0x1f800
|
||||
|
||||
#define HW_SSP_DEBUG(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x100))
|
||||
|
||||
#define HW_SSP_VERSION(ssp) (*(volatile uint32_t *)(HW_SSP_BASE(ssp) + 0x110))
|
||||
#define BM_SSP_CTRL1_TIMEOUT_IRQ \
|
||||
BM_OR3(SSP_CTRL1, RESP_TIMEOUT_IRQ, DATA_TIMEOUT_IRQ, RECV_TIMEOUT_IRQ)
|
||||
|
||||
#define IMX233_MAX_SSP_XFER_SIZE IMX233_MAX_SINGLE_DMA_XFER_SIZE
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue