len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2025-12-07 05:35:02 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions

rk27xx: Use slower memory timings at startup

Browse source 
Our decade+old defaults are reported to trigger a failure on
one user's IHIFI770c and IHIFI960, but work on their HM-603.
Backing CAS latency off from 2 to 3 appears to be sufficient.

What's interesting is that on paper, CL=2 should be easily attainable
due to our max RAM clock of 100MHz, well within the worst-case timings
of the EM639165 SDRAM.

So as an experiment, this code can go back to CL=2 when we change the
CPU+RAM clock speeds.  IF this still proves problematic, it will be
removed.

Change-Id: I4a8cfa0563c076e7f25d9599a19b454f590861cd
This commit is contained in:
Solomon Peachy 2025-11-28 07:08:28 -05:00
parent 3307b04eed
commit a6538abd16
1 changed files with 19 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

20
firmware/target/arm/rk27xx/system-rk27xx.c
View file

@ -117,8 +117,14 @@ void system_init(void)
WDTCON &= ~(1<<3); WDTCON &= ~(1<<3);
#ifndef BOOTLOADER #ifndef BOOTLOADER
/* SDRAM tweaks */ /* SDRAM tweaks. Note this assumes 100MHz AHB+SDRAM clock. */
MCSDR_MODE = (2<<4)|3; /* CAS=2, burst=8 */
#if !(defined(HM60X) || defined(HM801))
MCSDR_MODE = (3<<4)|3; /* CAS=3, burst=8(2^3) -- Safe but slower */
#else
MCSDR_MODE = (2<<4)|3; /* CAS=2, burst=8(2^3) -- Ideal but causes startup issues on (some?) IHIFI devices */
#endif
MCSDR_T_REF = (125*100) >> 3; /* 125/8 = 15.625 autorefresh interval */ MCSDR_T_REF = (125*100) >> 3; /* 125/8 = 15.625 autorefresh interval */
MCSDR_T_RFC = (64*100) / 1000; /* autorefresh period */ MCSDR_T_RFC = (64*100) / 1000; /* autorefresh period */
MCSDR_T_RP = 1; /* precharge period */ MCSDR_T_RP = 1; /* precharge period */
@ -232,9 +238,15 @@ void commit_discard_dcache_range (const void *base, unsigned int size)
} }
} }
#ifdef HAVE_ADJUSTABLE_CPU_FREQ #if !defined(BOOTLOADER) && defined(HAVE_ADJUSTABLE_CPU_FREQ)
static inline void set_sdram_timing(int ahb_freq) static inline void set_sdram_timing(int ahb_freq)
{ {
#if 1
if (ahb_freq > 100000000)
MCSDR_MODE = (3<<4)|3; /* CAS=3, burst=8(2^3) */
else
MCSDR_MODE = (2<<4)|3; /* CAS=2, burst=8(2^3) */
#endif
MCSDR_T_REF = (125*ahb_freq/1000000) >> 3; MCSDR_T_REF = (125*ahb_freq/1000000) >> 3;
MCSDR_T_RFC = (64*ahb_freq/1000000)/1000; MCSDR_T_RFC = (64*ahb_freq/1000000)/1000;
} }
@ -244,6 +256,8 @@ void set_cpu_frequency(long frequency)
if (cpu_frequency == frequency) if (cpu_frequency == frequency)
return; return;
/* Temporarily use more conservative SDRAM settings
so we don't glitch when changing clocks */
set_sdram_timing(12000000); set_sdram_timing(12000000);
if (frequency == CPUFREQ_MAX) if (frequency == CPUFREQ_MAX)