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PP502x: Get switch_thread back out of IRAM and devise a better core wakeup system that's not timing dependant. Hopefully something simpler will be found or devised eventually that meets all requirements. Rename mailbox-related registers.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15179 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
fffc257897
commit
a443614dd2
2 changed files with 102 additions and 54 deletions
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@ -387,13 +387,6 @@ void corelock_unlock(struct corelock *cl)
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#endif /* CONFIG_CORELOCK == SW_CORELOCK */
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#ifdef CPU_PP502x
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/* Some code relies on timing */
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void switch_thread(struct thread_entry *old) ICODE_ATTR;
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void core_wake(IF_COP_VOID(unsigned int othercore)) ICODE_ATTR;
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void core_idle(void) ICODE_ATTR;
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#endif
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/*---------------------------------------------------------------------------
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* Put core in a power-saving state if waking list wasn't repopulated and if
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* no other core requested a wakeup for it to perform a task.
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@ -403,34 +396,59 @@ static inline void core_sleep(IF_COP(unsigned int core,) struct thread_entry **w
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{
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#if NUM_CORES > 1
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#ifdef CPU_PP502x
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#if 1
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/* Disabling IRQ and FIQ is important to making the fixed-time sequence
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* non-interruptable */
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asm volatile (
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"mrs r2, cpsr \n" /* Disable IRQ, FIQ */
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"orr r2, r2, #0xc0 \n"
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"msr cpsr_c, r2 \n"
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"ldr r0, [%[w]] \n" /* Check *waking */
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"cmp r0, #0 \n" /* != NULL -> exit */
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"bne 1f \n"
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/* ------ fixed-time sequence ----- */ /* Can this be relied upon? */
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"ldr r0, [%[ms], %[oc], lsl #2] \n" /* Stay-awake requested? */
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"mov r1, #0x80000000 \n"
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"tst r0, #1 \n"
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"streq r1, [%[ct], %[c], lsl #2] \n" /* Sleep if not */
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"nop \n"
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"mov r0, #0 \n"
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"str r0, [%[ct], %[c], lsl #2] \n" /* Clear control reg */
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/* -------------------------------- */
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"1: \n"
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"mov r0, #1 \n"
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"add r1, %[ms], #8 \n"
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"str r0, [r1, %[oc], lsl #2] \n" /* Clear mailbox */
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"mov r0, #4 \n" /* r0 = 0x4 << core */
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"mov r0, r0, lsl %[c] \n"
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"str r0, [%[mbx], #4] \n" /* signal intent to sleep */
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"ldr r1, [%[waking]] \n" /* *waking == NULL ? */
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"cmp r1, #0 \n"
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"ldreq r1, [%[mbx], #0] \n" /* && !(MBX_MSG_STAT & (0x10<<core)) ? */
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"tsteq r1, r0, lsl #2 \n"
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"moveq r1, #0x80000000 \n" /* Then sleep */
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"streq r1, [%[ctl], %[c], lsl #2] \n"
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"moveq r1, #0 \n" /* Clear control reg */
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"streq r1, [%[ctl], %[c], lsl #2] \n"
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"orr r1, r0, r0, lsl #2 \n" /* Signal intent to wake - clear wake flag */
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"str r1, [%[mbx], #8] \n"
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"1: \n" /* Wait for wake procedure to finish */
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"ldr r1, [%[mbx], #0] \n"
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"tst r1, r0, lsr #2 \n"
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"bne 1b \n"
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"bic r2, r2, #0xc0 \n" /* Enable interrupts */
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"msr cpsr_c, r2 \n"
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:
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: [ct]"r"(&PROC_CTL(CPU)), [ms]"r"(&PROC_MESSAGE(CPU)),
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[c]"r" (core), [oc]"r"(1-core), [w]"r"(waking)
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:
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: [ctl]"r"(&PROC_CTL(CPU)), [mbx]"r"(MBX_BASE),
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[waking]"r"(waking), [c]"r"(core)
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: "r0", "r1", "r2");
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#else /* C version for reference */
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/* Disable IRQ, FIQ */
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set_interrupt_status(IRQ_FIQ_DISABLED, IRQ_FIQ_STATUS);
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/* Signal intent to sleep */
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MBX_MSG_SET = 0x4 << core;
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/* Something waking or other processor intends to wake us? */
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if (*waking == NULL && (MBX_MSG_STAT & (0x10 << core)) == 0)
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{
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PROC_CTL(core) = PROC_SLEEP; nop; /* Snooze */
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PROC_CTL(core) = 0; /* Clear control reg */
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}
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/* Signal wake - clear wake flag */
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MBX_MSG_CLR = 0x14 << core;
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/* Wait for other processor to finish wake procedure */
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while (MBX_MSG_STAT & (0x1 << core));
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/* Enable IRQ, FIQ */
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set_interrupt_status(IRQ_FIQ_ENABLED, IRQ_FIQ_STATUS);
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#endif /* ASM/C selection */
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#else
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/* TODO: PP5002 */
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#endif /* CONFIG_CPU == */
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@ -454,26 +472,52 @@ void core_wake(IF_COP_VOID(unsigned int othercore))
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#if NUM_CORES == 1
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/* No wakey - core already wakey */
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#elif defined (CPU_PP502x)
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#if 1
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/* avoid r0 since that contains othercore */
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asm volatile (
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"mrs r2, cpsr \n"
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"orr r1, r2, #0xc0 \n"
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"msr cpsr_c, r1 \n"
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"mov r1, #1 \n"
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/* ------ fixed-time sequence ----- */ /* Can this be relied upon? */
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"str r1, [%[ms], %[oc], lsl #2] \n" /* Send stay-awake message */
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"nop \n"
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"nop \n"
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"ldr r1, [%[ct], %[oc], lsl #2] \n" /* Wake other core if asleep */
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"tst r1, #0x80000000 \n"
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"bic r1, r1, #0x80000000 \n"
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"strne r1, [%[ct], %[oc], lsl #2] \n"
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/* -------------------------------- */
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"msr cpsr_c, r2 \n"
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"mrs r3, cpsr \n" /* Disable IRQ */
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"orr r1, r3, #0x80 \n"
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"msr cpsr_c, r1 \n"
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"mov r2, #0x11 \n" /* r2 = (0x11 << othercore) */
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"mov r2, r2, lsl %[oc] \n" /* Signal intent to wake othercore */
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"str r2, [%[mbx], #4] \n"
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"1: \n" /* If it intends to sleep, let it first */
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"ldr r1, [%[mbx], #0] \n" /* (MSG_MSG_STAT & (0x4 << othercore)) != 0 ? */
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"eor r1, r1, #0xc \n"
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"tst r1, r2, lsr #2 \n"
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"ldr r1, [%[ctl], %[oc], lsl #2] \n" /* && (PROC_CTL(othercore) & PROC_SLEEP) == 0 ? */
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"tsteq r1, #0x80000000 \n"
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"beq 1b \n" /* Wait for sleep or wake */
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"tst r1, #0x80000000 \n" /* If sleeping, wake it */
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"movne r1, #0x0 \n"
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"strne r1, [%[ctl], %[oc], lsl #2] \n"
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"mov r1, r2, lsr #4 \n"
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"str r1, [%[mbx], #8] \n" /* Done with wake procedure */
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"msr cpsr_c, r3 \n" /* Restore int status */
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:
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: [ct]"r"(&PROC_CTL(CPU)), [ms]"r"(&PROC_MESSAGE(CPU)),
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[oc]"r" (othercore)
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: "r1", "r2");
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: [ctl]"r"(&PROC_CTL(CPU)), [mbx]"r"(MBX_BASE), [oc]"r" (othercore)
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: "r1", "r2", "r3");
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#else /* C version for reference */
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/* Disable interrupts - avoid reentrancy from the tick */
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int oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL);
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/* Signal intent to wake other processor - set stay awake */
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MBX_MSG_SET = 0x11 << othercore;
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/* If it intends to sleep, wait until it does or aborts */
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while ((MBX_MSG_STAT & (0x4 << othercore)) != 0 &&
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(PROC_CTL(othercore) & PROC_SLEEP) == 0);
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/* If sleeping, wake it up */
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if (PROC_CTL(othercore) & PROC_SLEEP)
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{
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PROC_CTL(othercore) = 0;
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}
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/* Done with wake procedure */
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MBX_MSG_CLR = 0x1 << othercore;
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set_irq_level(oldlevel);
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#endif /* ASM/C selection */
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#else
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PROC_CTL(othercore) = PROC_WAKE;
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#endif
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@ -2496,6 +2540,7 @@ void init_threads(void)
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#if NUM_CORES > 1 /* This code path will not be run on single core targets */
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/* TODO: HAL interface for this */
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/* Wake up coprocessor and let it initialize kernel and threads */
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MBX_MSG_CLR = 0x3f;
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COP_CTL = PROC_WAKE;
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/* Sleep until finished */
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CPU_CTL = PROC_SLEEP;
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