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Apply FS#9650 (by Thomas Martitz). This adds hotswap and microSD support for the Fuze. It doesn't seem to work for all cards yet.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19447 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Frank Gevaerts 2008-12-15 23:37:16 +00:00
parent 1388bd3430
commit 9f37f04619
2 changed files with 105 additions and 18 deletions
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36
firmware/export/as3525.h
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@ -306,20 +306,48 @@ interface */
/* GPIO registers */
#define GPIOA_DIR (*(volatile unsigned char*)(GPIOA_BASE+0x400))
#define GPIOA_IS (*(volatile unsigned char*)(GPIOA_BASE+0x404))
#define GPIOA_IBE (*(volatile unsigned char*)(GPIOA_BASE+0x408))
#define GPIOA_IEV (*(volatile unsigned char*)(GPIOA_BASE+0x40C))
#define GPIOA_IE (*(volatile unsigned char*)(GPIOA_BASE+0x410))
#define GPIOA_RIS (*(volatile unsigned char*)(GPIOA_BASE+0x414))
#define GPIOA_MIS (*(volatile unsigned char*)(GPIOA_BASE+0x418))
#define GPIOA_IC (*(volatile unsigned char*)(GPIOA_BASE+0x41C))
#define GPIOA_AFSEL (*(volatile unsigned char*)(GPIOA_BASE+0x420))
#define GPIOA_PIN(a) (*(volatile unsigned char*)(GPIOA_BASE+4*(1<<(a))))
#define GPIOA_PIN(a) (*(volatile unsigned char*)(GPIOA_BASE+(1<<((a)+2))))
#define GPIOB_DIR (*(volatile unsigned char*)(GPIOB_BASE+0x400))
#define GPIOB_IS (*(volatile unsigned char*)(GPIOB_BASE+0x404))
#define GPIOB_IBE (*(volatile unsigned char*)(GPIOB_BASE+0x408))
#define GPIOB_IEV (*(volatile unsigned char*)(GPIOB_BASE+0x40C))
#define GPIOB_IE (*(volatile unsigned char*)(GPIOB_BASE+0x410))
#define GPIOB_RIS (*(volatile unsigned char*)(GPIOB_BASE+0x414))
#define GPIOB_MIS (*(volatile unsigned char*)(GPIOB_BASE+0x418))
#define GPIOB_IC (*(volatile unsigned char*)(GPIOB_BASE+0x41C))
#define GPIOB_AFSEL (*(volatile unsigned char*)(GPIOB_BASE+0x420))
#define GPIOB_PIN(a) (*(volatile unsigned char*)(GPIOB_BASE+4*(1<<(a))))
#define GPIOB_PIN(a) (*(volatile unsigned char*)(GPIOB_BASE+(1<<((a)+2))))
#define GPIOC_DIR (*(volatile unsigned char*)(GPIOC_BASE+0x400))
#define GPIOC_IS (*(volatile unsigned char*)(GPIOC_BASE+0x404))
#define GPIOC_IBE (*(volatile unsigned char*)(GPIOC_BASE+0x408))
#define GPIOC_IEV (*(volatile unsigned char*)(GPIOC_BASE+0x40C))
#define GPIOC_IE (*(volatile unsigned char*)(GPIOC_BASE+0x410))
#define GPIOC_RIS (*(volatile unsigned char*)(GPIOC_BASE+0x414))
#define GPIOC_MIS (*(volatile unsigned char*)(GPIOC_BASE+0x418))
#define GPIOC_IC (*(volatile unsigned char*)(GPIOC_BASE+0x41C))
#define GPIOC_AFSEL (*(volatile unsigned char*)(GPIOC_BASE+0x420))
#define GPIOC_PIN(a) (*(volatile unsigned char*)(GPIOC_BASE+4*(1<<(a))))
#define GPIOC_PIN(a) (*(volatile unsigned char*)(GPIOC_BASE+(1<<((a)+2))))
#define GPIOD_DIR (*(volatile unsigned char*)(GPIOD_BASE+0x400))
#define GPIOD_IS (*(volatile unsigned char*)(GPIOD_BASE+0x404))
#define GPIOD_IBE (*(volatile unsigned char*)(GPIOD_BASE+0x408))
#define GPIOD_IEV (*(volatile unsigned char*)(GPIOD_BASE+0x40C))
#define GPIOD_IE (*(volatile unsigned char*)(GPIOD_BASE+0x410))
#define GPIOD_RIS (*(volatile unsigned char*)(GPIOD_BASE+0x414))
#define GPIOD_MIS (*(volatile unsigned char*)(GPIOD_BASE+0x418))
#define GPIOD_IC (*(volatile unsigned char*)(GPIOD_BASE+0x41C))
#define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420))
#define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a))))
#define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+(1<<((a)+2))))
/* ARM PL172 Memory Controller registers */